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LRS1382 handle this document carefully for it contains material protected by international copyright law. any reproduction, full or in part, of this material is prohibited without the express written permission of the company. when using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. in no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1)the products covered herein are designed and manufactured for the following application areas. when using the products covered herein for the equipment listed in paragraph (2), even for the following application areas, be sure to observe the precautions given in paragraph (2). never use the products for the equipment listed in paragraph (3). ? office electronics ? instrumentation and measuring equipment ? machine tools ? audiovisual equipment ? home appliance ? communication equipment other than for trunk lines (2)those contemplating using the products covered herein for the following equipment which demands high reliability , should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. ? control and safety devices for airplanes, trains, automobiles, and other transportation equipment ? mainframe computers ? traffic control systems ? gas leak detectors and automatic cutoff devices ? rescue and security equipment ? other safety devices and safety equipment, etc. (3)do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. ? aerospace equipment ? communications equipment for trunk lines ? control equipment for the nuclear power industry ? medical equipment related to life support, etc. (4)please direct all queries and comments regarding the interpretation of the above three paragraphs to a sales representative of the company. please direct all queries regarding the products covered herein to a sales representative of the company.
LRS1382 1 contents 1. description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2simultaneous operation modes allowed with four planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4. block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5. command definitions for flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2identifier codes and otp address for read operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.3identifier codes and otp address for read operation on partition configuration. . . . . . . . . . . . . . . . . . . . . . 10 5.4otp block address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.5functions of block lockand block lock-down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.6block locking state transitions upon command write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.7block locking state transitions upon f-wp transition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6. status register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7. memory map for flash memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9. recommended dc operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 10. pin capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 11. dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 12. ac electrical characteristics for flash memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 12.1ac test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 12.2read cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 12.3write cycle (f-we / f-ce controlled). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 12.4block erase, full chip erase, (page buffer) program and otp program performance. . . . . . . . . . . . . . . . . . . 22 12.5flash memory ac characteristics timing chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 12.6reset operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 13. ac electrical characteristics for sram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 13.1ac test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 13.2read cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 13.3write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 13.4sram ac characteristics timing chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 14. data retention characteristics for sram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 15. notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 16. flash memory data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 17. design considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 18. related document information . . . . . . . . . . . . . . . . . . . . . . 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LRS1382 2 1.description the LRS1382 is a combination memory organized as 2,097,152 x16 bit flash memory and 524.288 x16 bit static ram in one package. features - power supply ? ? ? ? 2.7v to 3.3v - operating temperature ? ? ? ? -25 c to +85 c - not designed or rated as radiation hardened - 72pin csp (lcsp072-p-0811) plastic package - flash memory has p-type bulk silicon, and sram has p-type bulk silicon flash memory - access time ? ? ? ? 85 ns(max.) - power supply current (the current for f-v cc pin and f-v pp pin) read ? ? ? ? 25 ma(max. t cycle = 200ns, cmos input) word write ? ? ? ? 60 ma(max.) block erase ? ? ? ? 30 ma(max.) reset power-down ? ? ? ? 25 a(max. f-rst = gnd 0.2v, i out (f-ry/by ) = 0ma) standby ? ? ? ? 25 a (max. f-ce = f-rst = f-v cc 0.2v) - optimized array blocking architecture eight 4k-word parameter blocks sixty-three 32k-word main blocks top parameter location - extended cycling capability 100,000 block erase cycles(f-v pp = 2.7v to 3.3v) 1,000 block erase cycles and total 80 hours(f-v pp = 11.7v to 12.3v) - enhanced automated suspend options word write suspend to read block erase suspend to word write block erase suspend to read - otp block 4 word + 4 word array sram - access time ? ? ? ? 70 ns(max.) - power supply current operating current ? ? ? ? 50 ma(max. t rc , t wc = min.) ? ? ? ? 8 ma(max. t rc , t wc = 1 s, cmos input) standby current ? ? ? ? 25 a(max.) data retention current ? ? ? ? 25 a(max. s-v cc = 3.0v)
LRS1382 3 2.pin configuration index(top view)
LRS1382 4 pindescriptiontype a 0 to a 16 , a 18 address inputs (common)input f-a 17 , f-a 19 , f-a 20 address inputs (flash)input s-a 17 address input (sram)input f-ce chip enable inputs (flash)input s-ce 1 , s-ce 2 chip enable inputs (sram)input f-we write enable input (flash)input s-we write enable input (sram)input f-oe output enable input (flash)input s-oe output enable input (sram)input s-lb sram byte enable input (dq 0 to dq 7 ) input s-ub sram byte enable input (dq 8 to dq 15 ) input f-rst reset power down input (flash) block erase and write : v ih read : v ih reset power down : v il input f-wp write protect input (flash) when f-wp is v il , locked-down blocks cannot be unlocked. erase or program operation can be executed to the blocks which are not locked and locked-down. when f-wp is v ih , lock-down is disabled. input f-ry/by ready/busy output (flash) during an erase or write operation : v ol block erase and write suspend : high-z (high impedance) open drain output dq 0 to dq 15 data inputs and outputs (common)input / output f-v cc power supply (flash)power s-v cc power supply (sram)power f-v pp monitoring power supply voltage (flash) block erase and write : f-v pp = v pph1/2 all blocks locked : f-v pp < v pplk input gndgnd (common)power ncnon connection (should be all open)- t 1 to t 3 test pins (should be all open)-
LRS1382 5 3.truth table 3.1 bus operation (1) notes: 1.l = v il , h = v ih , x = h or l. high-z = high impedance. refer to the dc characteristics. 2.command writes involving block erase, full chip erase, (page buffer) program or otp program are reliably executed when f-v pp = v pph1/2 and f-v cc = 2.7v to 3.3 v . block erase, full chip erase, (page buffer) program or otp program with f-v pp < v pph1/2 (min.) produce spurious results and should not be attempted. 3.never hold f-oe low and f-we low at the same timing. 4.refer section 5. command definitions for flash memory valid d in during a write operation. 5.f-wp set to v il orv ih . 6.electricity consumption is lowest when f-rst = gnd 0.2v. 7.flash read mode 8. sram standby mode9. s-ub , s-lb control mode flashsramnotes f-ce f-rst f-oe f-we s-ce 1 s-ce 2 s-oe s-we s-lb s-ub dq 0 to dq 15 read standby 3,5 lh l h (8)xx(8) (7) output disable 5 h high-z write2,3,4,5l d in standby read5 hhxxlh lh(9) output disable 5 hhxx high-z xxhh write5xl(9) reset power down read5,6 xlxxlh lh(9) output disable 5,6 hhxx high-z xxhh write5,6xl(9) standby standby 5hh xx(8)xx(8)high-z reset power down 5,6xl modeaddress dq 0 to dq 15 read arrayx d out read identifier codes/otpsee 5.2, 5.3see 5.2, 5.3 read queryrefer to the appendixrefer to the appendix s-ce 1 s-ce 2 s-lb s-ub s-lb s-ub dq 0 to dq 7 dq 8 to dq 15 hxxxll d out /d in d out /d in xlxxlh d out /d in high-z xxhhhlhigh-z d out /d in
LRS1382 6 3.2simultaneous operation modes allowed with four planes (1, 2) notes: 1."x" denotes the operation available. 2.configurative partition dual work restrictions: status register reflects partition state, not wsm (write state machine) state - this allows a status register for each partition. only one partition can be erased or programmed at a time - no command queuing except page buffer program. commands must be written to an address within the block targeted by that command. if one partition is: then the modes allowed in the other partition is: read array read id/otp read status read query word program page buffer program otp program block erase full chip erase program suspend block erase suspend read arrayxxxxxxxxx read id/otpxxxxxxxxx read statusxxxxxxxxxxx read queryxxxxxxxxx word programxxxxx page buffer program xxxxx otp programx block erasexxxx full chip erasex program suspend xxxxx block erase suspend xxxxxxx
LRS1382 7 4.block diagram
LRS1382 8 5.command definitions for flash memory (11) 5.1command definitions notes: 1.bus operations are defined in 3.1 bus operation. 2.first bus cycle command address should be the same as the second cycle address. x=any valid address within the device. pa=address within the selected partition. ia=identifier codes address (see 5.2, 5.3). qa=query codes address. refer to the lh28f320bx, lh28f640bx series appendix for details. ba=address within the block being erased, set/cleared block lock bit or set block lock-down bit. wa=address of memory location for the program command or the first address for the page buffer program command. oa=address of otp block to be read or programmed (see 5.4 otp block address map). pcrc=partition configuration register code presented on the address a 0 -a 15 . 3.id=data read from identifier codes. (see 5.2, 5.3 ). qd=data read from query database. refer to the lh28f320bx, lh28f640bx series appendix for details. srd=data read from status register. see 6. status register definition for a description of the status register bits. wd=data to be programmed at location wa. data is latched on the rising edge of f-we or f-ce (whichever goes high first). od=data to be programmed at location oa. data is latched on the rising edge of f-we or f-ce (whichever goes high first). n-1=n is the number of the words to be loaded into a page buffer. 4.following the read identifier codes/otp command, read operations access manufacturer code, device code, block lock configuration code, partition configuration register code and the data within otp block (see 5.2, 5.3 ). the read query command is available for reading cfi (common flash interface) information. 5.block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. unlocked block can be erased or programmed when f-rst is v ih . command bus cycles req d notes first bus cyclesecond bus cycle oper (1) address (2) data (3) oper (1) address (2) data (3) read array12writepaffh read identifier codes/otp 22,3,4writepa90hreadia or oaid or od read query 22,3,4writepa98hreadqaqd read status register22,3writepa70hreadpasrd clear status register12writepa50h block erase22,3,5writeba20hwritebad0h full chip erase22,5,9writex30hwritexd0h program22,3,5,6writewa 40h or 10h writewawd page buffer program 42,3,5,7writewae8hwritewan-1 block erase and (page buffer) program suspend 12,8,9writepab0h block erase and (page buffer) program resume 12,8,9writepad0h set block lock bit22writeba60hwriteba01h clear block lock bit22,10writeba60hwritebad0h set block lock-down bit22writeba60hwriteba2fh otp program22,3,9writeoac0hwriteoaod set partition configuration register 22,3writepcrc60hwritepcrc04h
LRS1382 9 6.either 40h or 10h are recognized by the cui (command user interface) as the program setup. 7.following the third bus cycle, inputs the program sequential address and write data of "n" times. finally, input the any valid address within the target partition to be programmed and the confirm command (d0h). refer to the lh28f320bx, lh28f640bx series appendix for details. 8.if the program operation in one partition is suspended and the erase operation in other partition is also suspended, the suspended program operation should be resumed first, and then the suspended erase operation should be resumed next. 9.full chip erase and otp program operations can not be suspended. the otp program command can not be accepted while the block erase operation is being suspended. 10.following the clear block lock bit command, block which is not locked-down is unlocked when f-wp is v il . when f-wp is v ih , lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration. 11.commands other than those shown above are reserved by sharp for future device implementations and should not be used.
LRS1382 10 5.2identifier codes and otp address for read operation notes: 1.the address a 20 -a 16 to read the manufacturer, device, lock configuration, device configuration code and otp data are shown in below table. 2.top parameter device has its parameter blocks in the plane 3 (the highest address). 3.dq 15 -dq 2 is reserved for future implementation. 4.pcrc=partition configuration register code. 5.otp-lk=otp block lock configuration. 6.otp=otp block data. 5.3identifier codes and otp address for read operation on partition configuration (1) notes: 1.the address to read the identifier codes or otp data is dependent on the partition which is selected when writing the read identifier codes/otp command (90h). code address [a 15 -a 0 ] (1) data [dq 15 -dq 0 ] notes manufacturer codemanufacturer code0000h00b0h device code 32m topparameter device code 0001h00b4h2 block lock configuration code block is unlocked block address + 2 dq 0 = 0 3 block is lockeddq 0 = 1 3 block is not locked-downdq 1 = 0 3 block is locked-downdq 1 = 1 3 device configuration codepartition configuration register0006hpcrc4 otp otp lock0080hotp-lk5 otp 0081-0088hotp6 partition configuration registeraddress (32m-bit device) pcr.10pcr.9pcr.8 [a 20 -a 16 ] 00000h 00100h or 08h 01000h or 10h 10000h or 18h 01100h or 08h or 10h 11000h or 10h or 18h 10100h or 08h or 18h 11100h or 08h or 10h or 18h
LRS1382 11 5.4 otp block address map 5.5functions of block lock (1) and block lock-down note: 1.otp (one time program) block has the lock function which is different from those described above. 2.dq 0 = 1: a block is locked; dq 0 = 0: a block is unlocked. dq 1 = 1: a block is locked-down; dq 1 = 0: a block is not locked-down. 3.erase and program are general terms, respectively, to express: block erase, full chip erase and (page buffer) program operations. 4.at power-up or device reset, all blocks default to locked state and are not locked-down, that is, [001] (f-wp = 0) or [101] (f-wp = 1), regardless of the states before power-off or reset operation. 5.when f-wp is driven to v il in [110] state, the state changes to [011] and the blocks are automatically locked. current state erase/program allowed (3) statef-wp dq 1 (2) dq 0 (2) state name [000]000unlockedyes [001] (4) 001lockedno [011]011locked-downno [100]100unlockedyes [101] (4) 101lockedno [110] (5) 110lock-down disableyes [111]111lock-down disableno
LRS1382 12 5.6block locking state transitions upon command write (4) note: 1."set lock" means set block lock bit command, "clear lock" means clear block lock bit command and "set lock- down" means set block lock-down bit command. 2.when the set block lock-down bit command is written to the unlocked block (dq 0 = 0), the corresponding block is locked-down and automatically locked at the same time. 3."no change" means that the state remains unchanged after the command written. 4.in this state transitions table, assumes that f-wp is not changed and fixed v il or v ih . 5.7block locking state transitions upon f-wp transition (4) note: 1."f-wp = 0 1" means that f-wp is driven to v ih and "f-wp = 1 0" means that f-wp is driven to v il 2.state transition from the current state [011] to the next state depends on the previous state. 3.when f-wp is driven to v il in [110] state, the state changes to [011] and the blocks are automatically locked. 4.in this state transitions table, assumes that lock configuration commands are not written in previous, current and next state. current stateresult after lock command written (next state) statef-wp dq 1 dq 0 set lock (1) clear lock (1) set lock-down (1) [000]000[001]no change [011] (2) [001]001 no change (3) [000][011] [011]011no changeno changeno change [100]100[101]no change [111] (2) [101]101no change[100][111] [110]110[111]no change [111] (2) [111]111no change[110]no change previous state current stateresult after f-wp transition (next state) statef-wp dq 1 dq 0 f-wp = 0 1 (1) f-wp = 1 0 (1) -[000]000[100]- -[001]001[101]- [110] (2) [011]011 [110]- other than [110] (2) [111]- -[100]100-[000] -[101]101-[001] -[110]110- [011] (3) -[111]111-[011]
LRS1382 13 6.status register definition status register definition rrrrrrrr 15141312111098 wsmsbessbefcespbpopsvppspbpssdpsr 76543210 sr.15 - sr.8 = reserved for future enhancements (r) sr.7 = write state machine status (wsms) 1 = ready 0 = busy sr.6 = block erase suspend status (bess) 1 = block erase suspended 0 = block erase in progress/completed sr.5 = block erase and full chip erase status (befces) 1 = error in block erase or full chip erase 0 = successful block erase or full chip erase sr.4 = (page buffer) program and otp program status (pbpops) 1 = error in (page buffer) program or otp program 0 = successful (page buffer) program or otp program sr.3 = f-v pp status (vpps) 1 = f-v pp low detect, operation abort 0 = f-v pp ok sr.2 = (page buffer) program suspend status (pbpss) 1 = (page buffer) program suspended 0 = (page buffer) program in progress/completed sr.1 = device protect status (dps) 1 = erase or program attempted on a locked block, operation abort 0 = unlocked sr.0 = reserved for future enhancements (r) notes: status register indicates the status of the partition, not wsm (write state machine). even if the sr.7 is "1", the wsm may be occupied by the other partition when the device is set to 2, 3 or 4 partitions configuration. check sr.7 or f-ry/by to determine block erase, full chip erase, (page buffer) program or otp program completion. sr.6 - sr.0 are invalid while sr.7="0". if both sr.5 and sr.4 are "1"s after a block erase, full chip erase, page buffer program, set/clear block lock bit, set block lock-down bit or set read/partition configuration register attempt, an improper command sequence was entered. sr.3 does not provide a continuous indication of f-v pp level. the wsm interrogates and indicates the f-v pp level only after block erase, full chip erase, (page buffer) program or otp program command sequences. sr.3 is not guaranteed to report accurate feedback when f-v pp v pph1/2 or v pplk . sr.1 does not provide a continuous indication of block lock bit. the wsm interrogates the block lock bit only after block erase, full chip erase, (page buffer) program or otp pro- gram command sequences. it informs the system, depending on the attempted operation, if the block lock bit is set. reading the block lock configuration codes after writing the read iden- tifier codes/otp command indicates block lock bit status. sr.15 - sr.8 and sr.0 are reserved for future use and should be masked out when polling the status register.
LRS1382 14 extended status register definition rrrrrrrr 15141312111098 smsrrrrrrr 76543210 xsr.15-8 = reserved for future enhancements (r) xsr.7 = state machine status (sms) 1 = page buffer program available 0 = page buffer program not available xsr.6-0 = reserved for future enhancements (r) notes: after issue a page buffer program command (e8h), xsr.7=1 indicates that the entered command is accepted. if xsr.7 is "0", the command is not accepted and a next page buffer pro- gram command (e8h) should be issued again to check if page buffer is available or not. xsr.15-8 and xsr.6-0 are reserved for future use and should be masked out when polling the extended status register.
LRS1382 15 partition configuration register definition partition configuration rrrrrpc2pc1pc0 15141312111098 rrrrrrrr 76543210 pcr.15-11 = reserved for future enhancements (r) pcr.10-8 = partition configuration (pc2-0) 000 = no partitioning. dual work is not allowed. 001 = plane1-3 are merged into one partition. (default in a bottom parameter device) 010 = plane 0-1 and plane2-3 are merged into one partition respectively. 100 = plane 0-2 are merged into one partition. (default in a top parameter device) 011 = plane 2-3 are merged into one partition. there are three partitions in this configuration. dual work operation is available between any two partitions. 110 = plane 0-1 are merged into one partition. there are three partitions in this configuration. dual work operation is available between any two partitions. 101 = plane 1-2 are merged into one partition. there are three partitions in this configuration. dual work operation is available between any two partitions. 111 = there are four partitions in this configuration. each plane corresponds to each partition respectively. dual work operation is available between any two partitions. pcr.7-0 = reserved for future enhancements (r) notes: 1.after power-up or device reset, pcr10-8 (pc2-0) is set to "001" in a bottom parameter device and "100" in a top parameter device. 2.see the table below for more details. 3.pcr.15-11 and pcr.7-0 bits are reserved for future use. if these bits are read via the read identifier codes/otp command, the device may output "1" or "0" on these bits.
LRS1382 16 7.memory map for flash memory
LRS1382 17 8.absolute maximum ratings notes: 1.the maximum applicable voltage on any pins with respect to gnd. 2.except f-v pp . 3.-2.0v undershoot and v cc +2.0v overshoot are allowed when the pulse width is less than 20 nsec. 4.v in should not be over v cc +0.3v. 5.applying 12v 0.3v to f-v pp during erase/write can only be done for a maximum of 1000 cycles on each block. f-v pp may be connected to 12v 0.3v for total of 80 hours maximum. +12.6v overshoot is allowed when the pulse width is less than 20 nsec. 9.recommended dc operating conditions (t a = -25 c to +85 c) notes: 1.v cc is the lower of f-v cc or s-v cc . 2.v cc is the higher of f-v cc or s-v cc . 3.v cc includes both f-v cc and s-v cc . 10.pin capacitance (1) (t a = 25 c, f = 1mhz) note: 1.sampled but not 100% tested. symbolparameternotesratingsunit v cc supply voltage1,2-0.2 to +3.9v v in input voltage1,2,3,4 -0.2 to v cc +0.3 v t a operating temperature-25 to +85 c t stg storage temperature-55 to +125 c f-v pp f-v pp voltage 1,3,5-0.2 to +12.6v symbolparameternotesmin.typ.max.unit v cc supply voltage32.73.03.3v v ih input voltage v cc -0.4 (2) v cc +0.2 (1) v v il input voltage-0.20.4v symbolparameternotesmin.typ.max.unitcondition c in input capacitance15pf v in = 0v c i/o i/o capacitance25pf v i/o = 0v
LRS1382 18 11.dc electrical characteristics (1) dc electrical characteristics (t a = -25 c to +85 c, v cc = 2.7v to 3.3v) symbolparameternotesmin.typ.max.unittest conditions i li input load current 2 a v in = v cc or gnd i lo output leakage current 2 a v out = v cc or gnd i ccs f-v cc standby current 2420 a f-v cc = f-v cc max., f-ce = f-rst = f-v cc 0.2v, f-wp = f-v cc or gnd i ccas f-v cc automatic power savings current 2,5420 a f-v cc = f-v cc max., f-ce = gnd 0.2v, f-wp = f-v cc or gnd i ccd f-v cc reset power-down current 2420 a f-rst = gnd 0.2v i out (f-ry/by ) = 0ma i ccr average f-v cc read current normal mode 21525ma f-v cc = f-v cc max., f-ce = v il , f-oe = v ih , f = 5mhz i out = 0ma average f-v cc read current page mode 8 word read2510ma i ccw f-v cc (page buffer) program current 2,62060ma f-v pp = v pph1 2,61020ma f-v pp = v pph2 i cce f-v cc block erase, full chip erase current 2,61030ma f-v pp = v pph1 2,6515ma f-v pp = v pph2 i ccws i cces f-v cc (page buffer) program or block erase suspend current 2,310200 a f-ce = v ih i pps i ppr f-v pp standby or read current 2,725 a f-v pp f-v cc i ppw f-v pp (page buffer) program current 2,6,725 a f-v pp = v pph1 2,6,71030ma f-v pp = v pph2 i ppe f-v pp block erase, full chip erase current 2,6,725 a f-v pp = v pph1 2,6,7515ma f-v pp = v pph2 i ppws f-v pp (page buffer) program suspend current 2,725 a f-v pp = v pph1 2,710200 a f-v pp = v pph2 i ppes f-v pp block erase suspend current 2,725 a f-v pp = v pph1 2,710200 a f-v pp = v pph2
LRS1382 19 dc electrical characteristics (continue) (t a = -25 c to +85 c, v cc = 2.7v to 3.3v) notes: 1.v cc includes both f-v cc and s-v cc . 2.all currents are in rms unless otherwise noted. typical values at nominal v cc voltage and t a =+25 c. 3.i ccws and i cces are specified with the device de-selected. if read or (page buffer) program while in block erase suspend mode, the device s current draw is the sum of i ccws or i cces and i ccr or i ccw , respectively. 4.block erase, full chip erase, (page buffer) program and otp program are inhibited when f-v pp v pplk , and not guaranteed in the range between v pplk (max.) and v pph1 (min.) , between v pph1 (max.) and v pph2 (min.) and above v pph2 (max.). 5.the automatic power savings (aps) feature automatically places the device in power save mode after read cycle completion. standard address access timings (t avqv ) provide new data when addresses are changed. 6.sampled, not 100% tested. 7.f-v pp is not used for power supply pin. with f-v pp v pplk , block erase, full chip erase, (page buffer) program and otp program cannot be executed and should not be attempted. applying 12v 0.3v to f-v pp provides fast erasing or fast programming mode. in this mode, f-v pp is power supply pin and supplies the memory cell current for block erasing and (page buffer) programming. use similar power supply trace widths and layout considerations given to the v cc power bus. applying 12v 0.3v to f-v pp during erase/program can only be done for a maximum of 1000 cycles on each block. f-v pp may be connected to 12v 0.3v for a total of 80 hours maximum. symbolparameternotesmin. typ. (1) max.unitconditions i sb s-v cc standby current 225 a s-ce 1 , s-ce 2 s-v cc - 0.2v or s-ce 2 0.2v i sb1 s-v cc standby current 3ma s-ce 2 = v il i cc1 s-v cc operation current 50ma s-ce 1 = v il , s-ce 2 = v ih v in = v il or v ih t cycl = min i i/o = 0ma i cc2 s-v cc operation current 8ma s-ce 1 0.2v, s-ce s-v cc -0.2v, v in s-v cc -0.2v or 0.2v t cycl = 1 a i i/o = 0ma v il input low voltage6 -0.20.4 v v ih input high voltage6 v cc -0.4 v cc +0.2 v v ol output low voltage60.4v i ol = 0.5ma v oh output high voltage 6 v cc -0.2 v i oh = -0.5ma v pplk f-v pp lockout during normal operations 4,6,70.4v v pph1 f-v pp during block erase, full chip erase, word write or lock-bit configuration operations 1.6533.3v v pph2 711.71212.3v v lko f-v cc lockout voltage 1.5v
LRS1382 20 12.ac electrical characteristics for flash memory 12.1ac test conditions 12.2read cycle (t a = -25 c to +85 c, f-v cc = 2.7v to 3.3v) note: 1.sampled, not 100% tested. 2.f-oe may be delayed up to t elqv t glqv after the falling edge of f-ce without impact to t elqv . input pulse level0 v to 2.7 v input rise and fall time5 ns input and output timing ref. level1.35 v output load 1ttl + c l (50pf) symbolparameter notes min.max.unit t avav read cycle time85ns t avqv address to output delay85ns t elqv f-ce to output delay285ns t apa page address access time30ns t glqv f-oe to output delay220ns t phqv f-rst high to output delay150ns t ehqz , t ghqz f-ce or f-oe to output in high - z, whichever occurs first120ns t elqx f-ce to output in low - z10ns t glqx f-oe to output in low - z10ns t oh output hold from first occurring address, f-ce or f-oe change10ns
LRS1382 21 12.3write cycle (f-we / f-ce controlled) (1,2) (t a = -25 c to +85 c, f-v cc = 2.7v to 3.3v) notes: 1.the timing characteristics for reading the status register during block erase, full chip erase, (page buffer) program and otp program operations are the same as during read-only operations. see the ac characteristics for read cycle. 2.a write operation can be initiated and terminated with either f-ce or f-we . 3.sampled, not 100% tested. 4.write pulse width (t wp ) is defined from the falling edge of f-ce or f-we (whichever goes low last) to the rising edge of f-ce or f-we (whichever goes high first). hence, t wp =t wlwh =t eleh =t wleh =t elwh . 5.write pulse width high (t wph ) is defined from the rising edge of f-ce or f-we (whichever goes high first) to the falling edge of f-ce or f-we (whichever goes low last). hence, t wph =t whwl =t ehel =t whel =t ehwl . 6.f-v pp should be held at f-v pp =v pph1/2 until determination of block erase, full chip erase, (page buffer) program or otp program success (sr.1/3/4/5=0). 7.t whr0 (t ehr0 ) after the read query or read identifier codes/otp command=t avqv +100ns. 8.see 5.1 command definitions for valid address and data for block erase, full chip erase, (page buffer) program, otp program or lock bit configuration. symbolparameternotesmin.max.unit t phwl (t phel ) f-rst high recovery to f-we ( f-ce ) going low 3150ns t elwl (t wlel ) f-ce ( f-we ) setup to f-we (f-ce ) going low40ns t wlwh (t eleh ) f-we (f-ce ) pulse width460ns t dvwh (t dveh ) data setup to f-we (f-ce ) going high840ns t avwh (t aveh ) address setup to f-we (f-ce ) going high850ns t wheh (t ehwh ) f-ce ( f-we ) hold from f-we (f-ce ) high0ns t whdx (t ehdx ) data hold from f-we (f-ce ) high0ns t whax (t ehax ) address hold from f-we (f-ce ) high0ns t whwl (t ehel ) f-we (f-ce ) pulse width high530ns t shwh (t sheh ) f-wp high setup to f-we (f-ce ) going high30ns t vvwh (t vveh )f-v pp setup to f-we (f-ce ) going high 3200ns t whgl (t ehgl ) write recovery before read30ns t qvsl f-wp high hold from valid srd, f-ry/by high - z3, 60ns t qvvl f-v pp hold from valid srd, f-ry/by high - z 3, 60ns t whr0 (t ehr0 ) f-we (f-ce ) high to sr.7 going "0"3, 7 t avqv +40 ns t whrl (t ehrl ) f-we (f-ce ) high to f-ry/by going low3100ns
LRS1382 22 12.4block erase, full chip erase, (page buffer) program and otp program performance (4) (t a = -25 c to +85 c, f-v cc = 2.7v to 3.3v) notes: 1.typical values measured at t a =+25 c and nominal voltages. assumes corresponding lock bits are not set. subject to change based on device characterization. 2.excludes external system-level overhead. 3.every 16 words data are loaded alternatively into 2 page buffers. 4.sampled, but not 100% tested. 5.a latency time is required from writing suspend command (f-we or f-ce going high) until sr.7 going "1"or f-ry/by going high-z. 6.if the interval time from a block erase resume command to a subsequent block erase suspend command is shorter than t eres and its sequence is repeated, the block erase operation may not be finished. symbolparameternotes page buffer command is used or not used f-v pp =v pph1 (in system) f-v pp =v pph2 (in manufacturing) unit min. typ. (1) max. (2) min. typ. (1) max. (2) t wpb 4k-word parameter block program time 2not used0.050.30.040.12s 2, 3used0.030.120.020.06s t wmb 32k-word main block program time 2not used0.382.40.311s 2, 3used0.2410.170.5s t whqv1 / t ehqv1 word program time 2not used112009185 s 2, 3used7100590 s t whov1 / t ehov1 otp program time2not used3640027185 s t whqv2 / t ehqv2 4k-word parameter block erase time 2-0.340.24s t whqv3 / t ehqv3 32k-word main block erase time 2-0.650.55s t whrh1 / t ehrh1 (page buffer) program suspend latency time to read 5-510510 s t whrh2 / t ehrh2 block erase suspend latency time to read 5-520520 s t eres latency time from block erase resume command to block erase suspend command 6-500500 s
LRS1382 23 12.5flash memory ac characteristics timing chart ac waveform for single asynchronous read operations from status register, identifier codes, otp block or query code
LRS1382 24 ac waveform for asynchronous page mode read operations from main blocks or parameter blocks
LRS1382 25 ac waveform for write operations (f- we / f- ce controlled)
LRS1382 26 12.6reset operations (1,2) (t a = -25 c to +85 c, f-v cc = 2.7v to 3.3v) notes: 1.a reset time, t phqv , is required from the later of sr.7(f-ry/by ) going "1"(high-z) or f-rst going high until outputs are valid. see the ac characteristics - read cycle for t phqv . 2. t plph is <100ns the device may still reset but this is not guaranteed. 3.sampled, not 100% tested. 4. if f-rst asserted while a block erase, full chip erase, (page buffer) program or otp program operation is not executing, the reset will complete within 100ns. 5.when the device power-up, holding f-rst low minimum 100ns is required after f-v cc has been in predefined range and also has been in stable there. ac waveform for reset operation symbolparameternotesmin.max.unit t plph f-rst low to reset during read (f-rst should be low during power-up.) 1, 2, 3100ns t plrh f-rst low to reset during erase or program1, 3, 422 s t vph f-v cc 2.7v to f-rst high 1, 3, 5100ns t vhqv f-v cc 2.7v to output delay 31ms
LRS1382 27 13.ac electrical characteristics for sram 13.1ac test conditions note: 1.including scope and socket capacitance. 13.2read cycle (t a = -25 c to +85 c, s-v cc = 2.7v to 3.3v) note: 1.active output to high-z and high-z to output active tests specified for a 200mv transition from steady state levels into the test load. input pulse level0.4v to 2.2v input rise and fall time5ns input and output timing ref. level1.5 v output load 1ttl + c l (30pf) (1) symbolparameternotesmin.max.unit t rc read cycle time70ns t aa address access time70ns t ace1 chip enable access time (s-ce 1 ) 70ns t ace2 chip enable access time (s-ce 2 ) 70ns t be byte enable access time 70ns t oe outputenabletooutputvalid 40 ns t oh output hold from address change10ns t lz1 s-ce 1 low to output active 110ns t lz2 s-ce 2 high to output active 110ns t olz s-oe low to output active15ns t blz s-ub or s-lb low to output active15ns t hz1 s-ce 1 high to output in high-z 1025ns t hz2 s-ce 2 low to output in high-z 1025ns t ohz s-oe high to output in high-z1025ns t bhz s-ub or s-lb high to output in high-z1025ns
LRS1382 28 13.3write cycle (t a = -25 c to +85 c, s-v cc = 2.7v to 3.3v) note: 1.active output to high-z and high-z to output active tests specified for a 200mv transition from steady state levels into the test load. symbolparameternotesmin.max.unit t wc write cycle time70ns t cw chip enable to end of write60ns t aw address valid to end of write60ns t bw byte select time55ns t as address setup time0ns t wp write pulse width50ns t wr write recovery time0ns t dw input data setup time30ns t dh input data hold time0ns t ow s-we high to output active15ns t wz s-we low to output in high-z1025ns
LRS1382 29 13.4sram ac characteristics timing chart read cycle timing chart
LRS1382 30 write cycle timing chart (s- we controlled)
LRS1382 31 write cycle timing chart (s- ce controlled)
LRS1382 32 write cycle timing chart (s- ub , s- lb controlled)
LRS1382 33 14.data retention characteristics for sram (t a = -25 c to +85 c) notes 1.reference value at t a = 25 c, s-v cc = 3.0v. 2.s-ce 1 s-v cc - 0.2v, s-ce 2 s-v cc - 0.2v (s-ce 1 controlled) or s-ce 2 0.2v (s-ce 2 controlled). data retention timing chart (s- ce 1 controlled) (1) data retention timing chart (s-ce 2 controlled) symbolparameternotemin. typ. (1) max.unitconditions v ccdr data retention supply voltage21.53.3v s-ce 2 0.2v or s-ce 1 s-v cc - 0.2v i ccdr data retention supply current2225 a s-v cc = 3.0v s-ce 2 0.2v or s-ce 1 s-v cc - 0.2v t cdr chip enable setup time0ns t r chip enable hold time t rc ns
LRS1382 34 15.notes this product is a stacked csp package that a 32m (x16) bit flash memory and a 8m (x16) bit sram are assembled into. - supply power maximum difference (between f-v cc and s-v cc ) of the voltage is less than 0.3v. - power supply and chip enable of flash memory and sram (f-ce , s-ce 1 , s-ce 2 ) s-ce 1 should not be low and s-ce 2 should not be high when f-ce is low simultaneously. if the two memories are active together, possibly they may not operate normally by interference noises or data collision on dq bus. both f-v cc and s-v cc are needed to be applied by the recommended supply voltage at the same time expect sram data retention mode. - power up sequence when turning on flash memory power supply, keep f-rst low . after f-v cc reaches over 2.7v, keep f-rst low for more than 100nsec. - device decoupling the power supply is needed to be designed carefully because one of the sram and the flash memory is in standby mode when the other is active. a careful decoupling of power supplies is necessary between sram and flash memory. note peak current caused by transition of control signals (f-ce , s-ce 1 , s-ce 2 ).
LRS1382 35 16.flash memory data protection noises having a level exceeding the limit specified in the specification may be generated under specific operating conditions on some systems. such noises, when induced onto f-we signal or power supply, may be interpreted as false commands, causing undesired memory updating. to protect the data stored in the flash memory against unwanted writing, systems operating with the flash memory should have the following write protect designs, as appropriate. the below describes data protection method. 1.protecting data in specific block ? any locked block by setting its block lock bit is protected against the data alternation. when f-wp is v il , any locked- down block by setting its block lock-down bit is protected from lock status changes. by using this function, areas can be defined, for example, program area (locked blocks), and data area (unlocked blocks). ? for detailed block locking scheme, see chapter 5. command definitions for flash memory. 2.data protection through f-v pp ? when the level of f-v pp is lower than v pplk (lockout voltage), write operation on the flash memory is disabled. all blocks are locked and the data in the blocks are completely write protected. ? for the lockout voltage, refer to the specification. (see chapter 11. dc electrical characteristics) data protection during voltage transition 1.data protection thorough f-rst ? when the f-rst is kept low during power up and power down sequence, write operation on the flash memory is disabled, write protecting all blocks. ? for the details of f-rst control, refer to the specification. (see chapter 12.6 ac electrical characteristics for flash memory)
LRS1382 36 17.design considerations 1.power supply decoupling to avoid a bad effect to the system by flash memory power switching characteristics, each device should have a 0.1 f ceramic capacitor connected between its f-v cc and gnd and between its f-v pp and gnd. low inductance capacitors should be placed as close as possible to package leads. 2.f-v pp trace on printed circuit boards updating the memory contents of flash memories that reside in the target system requires that the printed circuit board designer pay attention to the f-v pp power supply trace. use similar trace widths and layout considerations given to the f- v cc power bus. 3.the inhibition of overwrite operation please do not execute reprograming 0 for the bit which has already been programed 0 . overwrite operation may generate unerasable bit. in case of reprograming 0 to the data which has been programed 1 . ? program 0 for the bit in which you want to change data from 1 to 0 . ? program 1 for the bit which has already been programed 0 . for example, changing data from 1011110110111101 to 1010110110111100 requires 1110111111111110 programing. 4.power supply block erase, full chip erase, word write and lock-bit configuration with an invalid f-v pp (see chapter 11. dc electrical characteristics) produce spurious results and should not be attempted. device operations at invalid f-v cc voltage (see chapter 11. dc electrical characteristics) produce spurious results and should not be attempted. 18.related document information (1) note: 1.international customers should contact their local sharp or distribution sales offices. document no.document name fum00701lh28f320bx, lh28f640bx series appendix

rev. 1.10 i a-1 recommended operating conditions a-1.1 at device power-up ac timing illustrated in figure a-1 is recommended for the supply voltages and the control signals at device power-up. if the timing in the figure is ignored, the device may not operate correctly. figure a-1.ac timing at device power-up for the ac specifications t vr , t r , t f in the figure, refer to the next page. see the ac electrical characteristics for flash memory described in specifications for the supply voltage range, the operating temperature and the ac specifications not shown in the next page.
rev. 1.10 ii a-1.1.1 rise and fall time notes: 1. sampled, not 100% tested. 2. this specification is applied for not only the device power-up but also the normal operations. t r (max.) and t f (max.) for f-rp (f-rst ) are tbd. symbolparameternotesmin.max.unit t vr f-v cc rise time 10.530000 s/v t r input signal rise time1, 2tbd t f input signal fall time1, 2tbd
rev. 1.10 iii a-1.2 glitch noises do not input the glitch noises which are below v ih (min.) or above v il (max.) on address, data, reset, and control signals, as shown in figure a-2 (b). the acceptable glitch noises are illustrated in figure a-2 (a). figure a-2.waveform for glitch noises see the dc electrical characteristics described in specifications for v ih (min.) and v il (max.).
rev. 1.10 iv a-2 related document information (1) note: 1. international customers should contact their local sharp or distribution sales office. document no.document name ap-001-sd-e flash memory family software drivers ap-006-pt-e data protection method of sharp flash memory ap-007-sw-e rp#, v pp electric potential switching circuit
north america europe asia sharp microelectronics of the americas 5700 nw pacific rim blvd. camas, wa 98607, u.s.a. phone: (360) 834-2500 fax: (360) 834-8903 http://www.sharpsma.com sharp microelectronics europe sonninstra ? e 3 20097 hamburg, germany phone: (49) 40 2376-2286 fax: (49) 40 2376-2232 http://www.sharpsme.com specifications are subject to change without notice. suggested applications (if any) are for standard use; see important restrictions for limitations on special applications. see limited warranty for sharp s product warranty. the limited warranty is in lieu, and exclusive of, all other warranties, express or implied. all express and implied warranties, including the warranties of merchantability, fitness for use and fitness for a particular purpose, are specifically excluded. in no event will sharp be liable, or in any way responsible, for any incidental or consequential economic or property damage. sharp corporation integrated circuits group 2613-1 ichinomoto-cho tenri-city, nara, 632, japan phone: +81-743-65-1321 fax: +81-743-65-1532 http://www.sharp.co.jp
page mode dual work flash memory 32m-bit, 64m-bit lh28f320bx, lh28f640bx series appendix fum00701 appendix no. jan.18,2001 issue: rev. a appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 handle this appendix carefully for it contains material protected by international copyright law. any reproduction, full or in part, of this material is prohibited without the express written permission of the company. when using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. in no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) the products covered herein are designed and manufactured for the following application areas. when using the products covered herein for the equipment listed in paragraph (2), even for the following application areas, be sure to observe the precautions given in paragraph (2). never use the products for the equipment listed in paragraph (3). office electronics instrumentation and measuring equipment machine tools audiovisual equipment home appliance communication equipment other than for trunk lines (2) those contemplating using the products covered herein for the following equipment which demands high reliability , should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. control and safety devices for airplanes, trains, automobiles, and other transportation equipment mainframe computers traffic control systems gas leak detectors and automatic cutoff devices rescue and security equipment other safety devices and safety equipment, etc. (3) do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. aerospace equipment communications equipment for trunk lines control equipment for the nuclear power industry medical equipment related to life support, etc. (4) please direct all queries and comments regarding the interpretation of the above three paragraphs to a sales representative of the company. please direct all queries regarding the products covered herein to a sales representative of the company. rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 1 rev. 2.20 contents page 1 introduction.............................................................. 2 1.1 features............................................................. 2 1.2 definition of block, plane and partition........... 2 1.3 product overview............................................. 2 1.4 product description........................................... 8 1.4.1 memory block organization..................... 8 1.4.2 four physical planes.................................. 8 1.4.3 partition...................................................... 8 1.4.4 parameter block......................................... 8 1.4.5 main block................................................. 8 1.4.6 otp (one time program) block................ 8 2 principles of operation.......................................... 14 2.1 operation mode after power-up or reset mode............................................. 14 2.2 read, program and erase operation............... 14 2.3 status register for each partition................... 14 2.4 data protection................................................ 14 3 bus operation........................................................ 15 3.1 read array...................................................... 15 3.2 output disable................................................ 15 3.3 standby............................................................ 15 3.4 reset................................................................ 15 3.5 read identifier codes/otp............................. 16 3.6 read query..................................................... 16 3.7 write the command to the cui...................... 16 4 command definitions............................................ 18 4.1 read array command.................................... 18 4.2 read identifier codes/otp command........... 18 4.3 read query command.................................... 23 4.4 read status register command...................... 23 4.5 clear status register command..................... 23 4.6 block erase command.................................... 26 4.7 full chip erase command.............................. 26 4.8 program command......................................... 31 4.9 page buffer program command..................... 31 4.10 block erase suspend command and block erase resume command........... 37 4.11 (page buffer) program suspend command and (page buffer) program resume command...................................... 39 4.12 set block lock bit command...................... 41 page 4.13 clear block lock bit command................... 44 4.14 set block lock-down bit command........... 44 4.15 otp program command............................... 46 4.16 set read configuration register command.................................................... 49 4.16.1 device read configuration.................... 49 4.16.2 frequency configuration....................... 51 4.16.3 data output configuration..................... 51 4.16.4 wait# configuration............................ 52 4.16.5 burst sequence....................................... 52 4.16.6 clock configuration............................... 52 4.16.7 burst wrap............................................. 52 4.16.8 burst length........................................... 52 4.16.8.1 continuous burst length................ 52 4.17 set partition configuration register command.................................................... 55 4.17.1 partition configuration.......................... 55 5 design considerations........................................... 57 5.1 hardware design considerations.................... 57 5.1.1 control using rst#, ce# and oe#......... 57 5.1.2 power supply decoupling....................... 57 5.1.3 vpp traces on printed circuit boards..... 57 5.1.4 vcc, vpp, rst# transitions.................. 57 5.1.5 power-up/down protection..................... 58 5.1.6 power dissipation.................................... 58 5.1.7 automatic power savings........................ 58 5.1.8 reset operation........................................ 58 5.2 software design considerations..................... 59 5.2.1 wsm (write state machine) polling....... 59 5.2.2 attention to program operation............... 59 5.3 data protection method.................................. 59 5.4 high performance read mode........................ 60 5.4.1 cpu compatibility................................... 60 5.4.2 features of adv# and clk.................... 60 5.4.3 address latch.......................................... 60 5.4.4 using asynchronous page mode............. 60 5.4.5 using synchronous burst mode.............. 61 5.4.6 using wait# in burst mode................... 61 5.4.7 single read mode.................................... 61 6 common flash interface........................................ 67 7 related document information.............................. 68 synchronous burst mode will be available for future device. appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 2 1 introduction this appendix describes how to use the lh28f320bx/ lh28f640bx series, synchronous/page mode dual work flash memory. section 1 outlines the lh28f320bx/lh28f640bx series. sections 2, 3, 4 and 5 describe the memory organization and functionality. when designing a specific system, take into design considerations described in section 5. 1.1 features synchronous/page mode dual work flash memory lh28f320bx/lh28f640bx series has the following features: ? dual work operation ? flexible partition configuration ? high performance asynchronous reads and synchronous burst reads ? page buffer program ? individual block locking and all blocks locked on power-up ? 8-word otp (one time program) block ? low power consumption ? parameter block architecture 1.2 definition of block, plane and partition block, plane and partition are defined and used in this document as explained below. ? block main block: 32k words. parameter block: 4k words. 32m-bit device has 8 parameter blocks and 63 main blocks. 64m-bit device has 8 parameter blocks and 127 main blocks. ? plane: 32m-bit and 64m-bit devices are divided into four physical planes (see table 1). plane0 or plane3 contains parameter blocks and main blocks. plane1 and plane2 consist of only main blocks. ? partition: read operation can be done in one partition while program/erase operation is being done in another partition. partition contains at least one plane or up to four planes. partition boundaries can be flexibly set to any plane boundary by the set partition configuration register command. if the partition configuration register is set to "111" (4 plane dual work mode), the partition is exactly the same as a plane. see section 4.17 for more information. table 1.address range of each plane 1.3 product overview synchronous/page mode dual work flash memory lh28f320bx/lh28f640bx series is capable of dual work operation: erase or program operation on one partition and read operation on other partitions (see table 2). the partition to be accessed is automatically identified according to the input address. dual work operations can be achieved by dividing the memory array into four physical planes as shown in figure 2.1 through figure 3.2. each plane is exactly one quarter of the entire memory array. the device has also virtual partitions. several planes can be flexibly merged to one partition by writing the set partition configuration register command. this feature allows the user to read from one partition even though one of the other partitions is executing an erase or program operation. if the device is set to the 4 partitions configuration, each partition is exactly the same as each physical plane. after power-up or device reset, plane 0-2 are merged into one partition for top parameter devices and plane1-3 are merged into one partition for bottom parameter devices. during dual work operation, read operations to the partition being erased or programmed access the status register which indicates whether the erase or program operation is successfully completed or not. dual work operation cannot be executed during full chip erase and otp program mode. memory array data can be read in two ways, that is, asynchronous 8-word page mode or synchronous burst mode. the default after power-up or device reset is the asynchronous read mode in which 8-word page mode is available. the user must set the read configuration register to enable the synchronous burst mode by writing the set read configuration register command. clk is then used to increment the internal burst address generator, synchronize with the host, and deliver data every clock cycle. the wait# output pin is used to signal plane # contains the blocks within the following address 32m bit64m bit plane 0000000h-07ffffh000000h-0fffffh plane 1080000h-0fffffh100000h-1fffffh plane 2100000h-17ffffh200000h-2fffffh plane 3180000h-1fffffh300000h-3fffffh rev. 2.20 synchronous burst mode will be available for future device. appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 3 that a burst is in progress. the synchronous burst feature cannot cross partition boundaries. the lh28f320bx/lh28f640bx series contains a page buffer of 16-word 2 plane. in the page buffer program mode, the data to be programmed is first stored into the page buffer before being transferred to the memory array. a page buffer program has high speed program performance. the page buffer program operation programs up to 16 word 2 data at sequential addresses within one block. that is, this operation cannot be used to program data at addresses separated by something even in the same block, or divided into different blocks. page buffer program cannot be applied to otp block described later in this section. for the parameter blocks and main blocks, individual block locking scheme that allows any block to be locked, unlocked or locked-down with no latency. the time required for block locking is less than the minimum command cycle time (minimum time from the rising edge of ce# or we# to write the command to the next rising edge of ce# or we#). the block is locked via the set block lock bit command or set block lock-down bit command. block erase, full chip erase and (page buffer) program operation cannot be executed for locked block, to protect codes and data from unwanted operation due to noises, etc.when the wp# pin is at v il , the locked-down block cannot be unlocked. when wp# pin is at v ih , lock- down bits are disabled and any block can be locked or unlocked through software. after wp# goes v il , any block previously marked lock-down revert to that state. at power-up or device reset, all blocks default to locked state and are not locked-down, regardless of the states before power-off or reset operation. this means that all write operations on any block are disabled. unauthorized use of cellular phone, communication device, etc. can be avoided by storing a security code into the 8-word otp (one time program) block (see figure 4) provided in addition to the parameter and main blocks. to ensure high reliability, a lock function for the otp block is provided. the lh28f320bx/lh28f640bx series has a v pp pin which monitors the level of the power supply voltage. when v pp v pplk , memory contents cannot be altered and the data in all blocks are completely write protected (see note 1) . note that the v pp is used only for checking the supply voltage, not used for device power supply pin. automatic power savings (aps) is the low power features to help increase battery life in portable applications. aps mode is initiated shortly after read cycle completion. in this mode, its current consumption decreases to the value equivalent of that in the standby mode. standard address access timings (t avqv ) provide new data when addresses are changed. during dual work operation (one partition being erased or programmed, while other partitions are read modes), the device cannot enter the automatic power savings mode if the input address remains unchanged. a cui (command user interface) serves as the interface between the system processor and internal operation of the device. a valid command sequence written to the cui initiates device automation. lh28f320bx/lh28f640bx series uses an advanced wsm (write state machine) to automatically execute erase and program operations within the memory array. the wsm is controlled through the cui. by writing a valid command sequence to the cui, the wsm is instructed to automatically handle the sequence of internal events and timings required to block erase, full chip erase, (page buffer) program or otp program operations. status registers are prepared for each partition to indicate the status of the partition. even if the wsm is occupied by executing erase or program operation in one partition, the status register of other partition reports that the device is not busy when the device is set to 2, 3 or 4 partitions configuration. when the rst# pin is at v il , reset mode is enabled which minimizes power consumption and provides write protection. the rst# is also useful for resetting the wsm to read array mode and initializing the status register bits to "80h". during power-on/off or transitions, keep the rst# pin at v il level to protect the data from noises, and initialize the device s internal control circuit. (note 1) please note following: ? for the lockout voltage v pplk to inhibit all write functions, refer to specifications. ? v pp should be kept lower than v pplk (gnd) during read operations to protect the data in all blocks. rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 4 a reset time (t phqv ) is required from rst# switching high until outputs are valid. likewise, the device has a wake time (t phwl , t phel ) from rst#-high until writes to the cui are recognized. erase operation erases one block or all blocks. programming is executed in either one word increments or by page sized increments using the high speed program page buffers. these operations use an industry standard set of cui command sequences. suspend commands exist for both the erase and program operations to permit the system to interrupt an erase or program operation in progress to enable the access to another memory location in the same partition. nested suspend is also supported. this allows the software to suspend an erase in one partition, start programming in a second partition, suspend programming in the second partition, then read from the second partition. after reading from the second partition, resume the suspended program in the second partition, then resume the suspended erase in the first partition. figure 1 shows the block diagram for lh28f320bx/ lh28f640bx series. the example of pin descriptions are explained in table 3.1 and table 3.2. notes: 1. "x" denotes the operation available. 2. configurative partition dual work restrictions: status register reflects partition state, not wsm(write state machine) state - this allows a status register for each partition. only one partition can be erased or programmed at a time - no command queuing except page buffer program. commands must be written to an address within the block targeted by that command. it is not possible to do burst reads that cross partition boundaries. table 2.simultaneous operation modes allowed with four planes (1, 2) if one partition is: then the modes allowed in the other partition is: read array read id/otp read status read query word program page buffer program otp program block erase full chip erase program suspend block erase suspend read arrayxxxxxxxxx read id/otpxxxxxxxxx read statusxxxxxxxxxxx read queryxxxxxxxxx word programxxxxx page buffer program xxxxx otp programx block erasexxxx full chip erasex program suspend xxxxx block erase suspend xxxxxxx rev. 2.20 appendix to spec no.: mfm-j13222 model no.: LRS1382 march 1, 2001
fum00701 5 figure 1.block diagram rev. 2.20 synchronous burst mode will be available for future device. appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 6 table 3.1.pin descriptions symboltypename and function a 0 -a 20 input address inputs: inputs for addresses. 32m: a 0 -a 20 a 0 -a 21 input address inputs: inputs for addresses. 64m: a 0 -a 21 dq 0 -dq 15 input/ output data input/outputs: inputs data and commands during cui (command user interface) write cycles, outputs data during memory array, status register, query, identifier code and device configuration code reads. data pins float to high-impedance (high z) when the chip or outputs are deselected. data is internally latched during an erase or program cycle. ce#input chip enable: activates the device s control logic, input buffers, decoders and sense amplifiers. ce#-high (v ih ) deselects the device and reduces power consumption to standby levels. clkinput clock: synchronizes the memory to the system bus operating frequency in synchronous burst mode. the first rising (or falling if rcr.6 is "0") edge latches the address when adv# is v il or upon a rising adv# edge. this is used only for synchronous burst mode. adv#input address valid: addresses are input to the memory when adv# is low (v il ). addresses are latched on adv# s rising edge during read and write operations. rst#input reset: when low (v il ), rst# resets internal automation and inhibits write operations which provides data protection. rst#-high (v ih ) enables normal operation. after power-up or reset mode, the device is automatically set to asynchronous read array mode. rst# must be low during power-up. oe#inputoutput enable: gates the device s outputs during a read cycle. we#input write enable: controls writes to the cui and array blocks. addresses and data are latched on the rising edge of ce# or we# (whichever goes high first). wp#input write protect: when wp# is v il , locked-down blocks cannot be unlocked. erase or program operation can be executed to the blocks which are not locked and locked- down. when wp# is v ih , lock-down is disabled. wait#output wait: outputs data valid status in synchronous burst mode while oe# is asserted. when high (v oh ) during a burst mode, data is valid. wait# low (v ol ) indicates invalid data. wait# is pulled high (v oh ) by an internal resister. the wait# signals of the multiple devices can be tied together to drive one system wait# signal. wait# is used only for synchronous burst mode. it also works during a continuous burst mode or 4-, 8- word burst with no-wrap (rcr.3="1") mode rev. 2.20 synchronous burst mode will be available for future device. appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 7 table 3.2.pin descriptions (continued) v pp input monitoring power supply voltage: v pp is not used for power supply pin. with v pp v pplk , block erase, full chip erase, (page buffer) program or otp program cannot be executed and should not be attempted. applying 12v 0.3v to v pp provides fast erasing or fast programming mode. in this mode, v pp is power supply pin. applying 12v 0.3v to v pp during erase/program can only be done for a maximum of 1000 cycles on each block. v pp may be connected to 12v 0.3v for a total of 80 hours maximum. use of this pin at 12v beyond these limits may reduce block cycling capability or cause permanent damage. v cc supply device power supply (see specifications): with v cc v lko , all write attempts to the flash memory are inhibited. device operations at invalid v cc voltage (see dc characteristics) produce spurious results and should not be attempted. v ccq supply input/output power supply (see specifications): power supply for all input/ output pins. gndsupplyground: do not float any ground pins. ncno connect: lead is not internally connected; it may be driven or floated. rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 8 1.4 product description 1.4.1 memory block organization the device is divided into four physical planes and the partitions can be flexibly configured by the set partition configuration register command. this allows dual work operations, that is, simultaneous read-while-erase and read-while-program operations. for the address locations of the blocks, see the memory map in figure 2.1 through figure 3.2. 1.4.2 four physical planes lh28f320bx/lh28f640bx series has four physical planes (one parameter plane and three uniform planes). each plane consists of 8m-bit (32m-bit device) or 16m- bit (64m-bit device) flash memory. the parameter plane consists of eight 4k-word parameter blocks and fifteen (32m-bit device) or thirty-one (64m-bit device) 32k- word main blocks. each uniform plane consists of sixteen (32m-bit device) or thirty-two (64m-bit device) 32k- word main blocks. each block can be erased independently up to 100,000 times. 1.4.3 partition partition boundaries can be configured by the set partition configuration register command. dual work operation can be done in two partitions. see partition configuration in table 17 and figure 17 for more detail. only one partition can be erased or programmed at a time and burst reads cannot cross partition boundaries. simultaneous operation modes are shown in table 2. 1.4.4 parameter block eight 4k-word parameter blocks within the parameter partition are provided as the memory area to facilitate storage of frequently update small parameters that would normally be stored in eeprom. by using software techniques, the word-rewrite functionality of eeproms can be emulated. the protection of the parameter block is controlled using a combination of the v pp , rst#, wp#, block lock bit and block lock-down bit. 1.4.5 main block 32k-word main blocks can store code and/or data. the protection of the main block is also controlled using a combination of the v pp , rst#, wp#, block lock bit and block lock-down bit. 1.4.6 otp (one time program) block the otp block is a special block that cannot be erased in order to secure the high system reliability. this 8-word (128-bit) otp block is independent of the 32m-bit or 64m-bit memory area. figure 4 shows the otp block address map. the otp block is divided into two areas. one is a factory programmed area where a unique number has been programmed in sharp factory. this factory programmed area is "read only" (already locked). the other is a customer programmable area that can be available for customers. this customer programmable area can also be locked. after locking, this customer programmable area is protected permanently. the data within the otp block can be read by the read identifier codes/otp command (90h). to return to read array mode, write the read array command (ffh) to the cui. the otp block bits are programmed by writing the otp program command (c0h) to the cui. write the otp program command (c0h) at the 1st command cycle and then write the address and the data at the 2nd cycle. if the otp program operation is failed, the status register bit sr.4 is set to "1". if the otp block is locked, the status register bits sr.4 and sr.1 are set to "1". the otp block can be locked using the otp program command (c0h). write the otp program command (c0h) at the 1st command cycle and then write the data (fffdh) to the lock location (80h) at the 2nd cycle. read cycle from address (80h) indicates the lockout state of the otp block. bit 0 of address (80h) means the factory programmed area lock state ("1" is "not locked" and "0" is "locked"). bit 1 of address (80h) means the customer programmable lock state. otp block lockout state is not reversible. unlike the main array block lock configuration, the lock state of the otp block is kept unchanged even if the power is turned off or reset operation is performed. the otp program command is only available for programming the otp block. page buffer program operations are available for the main array. otp program cannot be suspended through the (page buffer) program suspend command (described later). dual work operation cannot be executed during otp program. rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 9 figure 2.1.memory map for lh28f320bx series (top parameter) rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 10 figure 2.2.memory map for lh28f320bx series (bottom parameter) rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 11 figure 3.1.memory map for lh28f640bx series (top parameter) rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 12 figure 3.2.memory map for lh28f640bx series (bottom parameter) rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 13 figure 4.otp block address map for otp program (1, 2) (the area outside 80h~88h cannot be used.) notes: 1. a 21 is not used for 32m-bit device. 2. refer to table 6 through table 8 as to the otp block address map for read operation. rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 14 2 principles of operation synchronous/page mode dual work flash memory lh28f320bx/lh28f640bx series includes an on-chip wsm (write state machine) and can automatically execute block erase, full chip erase, (page buffer) program or otp program operation after writing the proper command to the cui (command user interface). 2.1 operation mode after power-up or reset mode after initial power-up or reset mode (refer to bus operation in section 3), the device defaults to the following mode. ? asynchronous read mode in which 8-word page mode is available ? plane 0-2 are merged into one partition for top parameter devices and plane1-3 are merged into one partition for bottom parameter devices. ? all blocks default to locked state and are not locked- down. manipulation of external memory control pins (ce#, oe#) allow read array, standby and output disable modes. 2.2 read, program and erase operation independent of the v pp voltage, the memory array, status register, identifier codes, otp block and query codes can be accessed. and also, set/clear block lock configuration, set read configuration register and set partition configuration register are available even if the v pp voltage is lower than v pplk . applying the specified voltage on v cc and v pph1/2 on v pp enables successful block erase, full chip erase, (page buffer) program and otp program operation. all functions associated with altering memory contents, which is block erase, full chip erase, (page buffer) program and otp program, are accessed via the cui and verified through the status register. commands are written using standard microprocessor write timings. addresses and data are internally latched on the rising edge of ce# or we# whichever goes high first during command write cycles. the cui contents serve as input to the wsm, which controls block erase, full chip erase, (page buffer) program and otp program. the internal algorithms are regulated by the wsm, including pulse repetition, internal verification and margining of data. writing the appropriate command outputs array data, status register data, identifier codes, lock configuration codes, device configuration codes, data within the otp block and query codes. in any block, the user can store an interface software that initiates and polls progress of block erase or (page buffer) program. because the lh28f320bx/lh28f640bx series has dual work function, data can be read from the partition not being erased or programmed without using the block erase suspend or (page buffer) program suspend. when the target partition is being erased or programmed, block erase suspend or (page buffer) program suspend allows system software to read/program data from/to blocks other than that which is suspended. 2.3 status register for each partition the lh28f320bx/lh28f640bx series has status registers for each partition. the 8-bit status register is available to monitor the partition state, or the erase or program status. status register indicates the status of the partition, not wsm. even if the status register bit sr.7 is "1", the wsm may be occupied by the other partition when the device is set to 2, 3 or 4 partitions configuration. the status register reports if an erase or program operation to each partition has been successfully completed, and if not, indicates a reason for the error. this register cannot be set, only can be cleared by writing the clear status register command or by resetting the device. 2.4 data protection block lock bit and block lock-down bit can be set for each block, to protect the data within its block. if the rst# is driven low (v il ), or if the voltage on the v cc pin is below the write lock out voltage (v lko ), or if the voltage on the v pp pin is below the write lock out voltage (v pplk ), then all write functions including otp program are disabled. the system should be designed to switch the voltage on v pp below the write lock out voltage (v pplk ) for read cycles. this scheme provides the data protection at the hardware level. the two-cycle command sequence architecture for block erase, full chip erase, (page buffer) program, otp program, and block lock configuration provides the data protection at the software level against data alternation. rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 15 3 bus operation the system cpu reads and writes the flash memory. all bus cycles to or from the flash memory conform to standard microprocessor bus cycles. table 4 lists the bus operation. 3.1 read array lh28f320bx/lh28f640bx series has seven control pins (clk, ce#, oe#, adv#, we#, rst# and wp#). when rst# is v ih , read operations access the memory array, status register, identifier codes, otp block and query codes independent of the voltage on v pp . the device is automatically initialized upon power-up or device reset mode and set to asynchronous read mode in which 8-word page mode is available. as necessary, write the appropriate read command (read array, read identifier codes/otp, read query or read status register command) with the partition address to the cui (command user interface). the cui decodes the partition address and set the target partition to the appropriate read mode. synchronous burst mode can be set by writing the set read configuration register command. it is impossible to set one partition to asynchronous read mode and other partition to synchronous burst mode at a time. asynchronous page mode and synchronous burst mode are available only for main array, that is, parameter blocks and main blocks. read operations for status register, identifier codes, otp block and query codes support single asynchronous read cycle or single synchronous read cycle. to read data from the lh28f320bx/lh28f640bx series, rst# and we# must be at v ih , and ce# and oe# at v il . adv# must be driven v il to fetch address. ce# is the device selection control, and ce#-low enables the selected memory device. oe# is the data output (dq 0 - dq 15 ) control and oe#-low drives the selected memory data onto the i/o bus. 3.2 output disable with oe# at v ih , the device outputs are disabled. output pins dq 0 - dq 15 are placed in a high-impedance (high z) state. 3.3 standby ce# at a logic-high level (v ih ) places the lh28f320bx/ lh28f640bx series in standby mode. in standby mode, the lh28f320bx/lh28f640bx series substantially reduces its power consumption because almost of all internal circuits are inactive. dq 0 -dq 15 outputs a high z state independent of oe#. even if ce# is set to v ih during block erase, full chip erase, (page buffer) program or otp program, the device continues the operation and consumes active power until the completion of the operation. 3.4 reset driving rst# to logic-low level (v il ) places the lh28f320bx/lh28f640bx series in reset mode. if rst# is held v il for a minimum t plph in read modes, the device is deselected and internal circuitry is turned off. outputs are placed in a high z state. status register is set to 80h. time t phqv is required after return from reset mode until initial memory access outputs are valid. after this wake-up interval, normal operation is restored. the device returns to the initial mode described in section 2.1. during block erase, full chip erase, (page buffer) program or otp program mode, rst#-low will abort the operation. memory contents being altered are no longer valid; the data may be partially erased or programmed. status register bit sr.7 remains "0" until the reset operation has been completed. after rst# goes to v ih , time t phwl and t phel is required before another command can be written. as with any automated device, it is important to assert rst# during system reset. when the system comes out of reset, it expects to read the data from the flash memory. lh28f320bx/lh28f640bx series allows proper cpu initialization following a system reset through the use of the rst# input. in this application, rst# is controlled by the same reset# signal that resets the system cpu. after return from reset mode, the lh28f320bx/ lh28f640bx series is automatically set to asynchronous read mode in which 8-word page mode is available. delay time t phqv is required until memory access outputs are valid. rev. 2.20 synchronous burst mode will be available for future device. appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 16 rev. 2.20 notes: 1. refer to dc characteristics. when v pp v pplk , memory contents can be read, but cannot be altered. 2. x can be v il or v ih for control pins and addresses, and v pplk or v pph1/2 for v pp . see dc characteristics for v pplk and v pph1/2 voltages. 3. rst# at gnd 0.2v ensures the lowest power consumption. 4. command writes involving block erase, full chip erase, (page buffer) program or otp program are reliably executed when v pp =v pph1/2 and v cc is the specified voltage. 5. refer to table 5 for valid d in during a write operation. 6. never hold oe# low and we# low at the same timing. 7. refer to appendix of lh28f320bx/lh28f640bx series for more information about query code. 3.5 read identifier codes/otp the manufacturer code, device code, block lock configuration codes, read configuration register code, partition configuration register code and the data within the otp block can be read in the read identifier codes/ otp mode (see table 6 through table 8). using the manufacturer and device codes, the system cpu can automatically match the device with its proper algorithms. 3.6 read query cfi (common flash interface) code, which is called query code, can be read after writing the read query command. the address to read query code should be in the partition address which is written with the read query command. the cfi data structure contains information such as block size, density, command set and electrical specifications (see section 6). in this mode, read cycles retrieve cfi information. to return to read array mode, write the read array command (ffh) with the partition address. 3.7 write the command to the cui except for the full chip erase command, writing commands to the cui always requires the word address, block address or partition address. before writing the block erase command, full chip erase command, (page buffer) program command or otp program command, wsm (write state machine) should be ready and not be used in any partition. table 4.bus operation (1, 2) modenotesrst#ce#oe#we#addressv pp dq 0-15 read array6v ih v il v il v ih xxd out output disablev ih v il v ih v ih xxhigh z standbyv ih v ih xxxxhigh z reset3v il xxxxxhigh z read identifier codes/otp6 v ih v il v il v ih see table 6 through table 8 x see table 6 through table 8 read query6,7 v ih v il v il v ih see section 6 x see section 6 write4,5,6v ih v il v ih v il xxd in appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 17 applying the specified voltage on v cc and v pph1/2 on v pp enables successful block erase, full chip erase, (page buffer) program or otp program with writing the proper command and address to the cui. erase or program operation may occur in only one partition at a time. other partitions must be in one of the read modes. the block erase command requires appropriate command and an address within the block to be erased. the full chip erase command requires appropriate command. the (page buffer) program command requires appropriate command and an address of the location to be programmed. the set/clear block lock bit or set block lock-down bit command requires appropriate command and an address within the target block. the otp program command requires appropriate command and an address of the location to be programmed within the otp block. the set read configuration register command or the set partition configuration register command requires appropriate command and configuration register code presented on the addresses a 0 -a 15 . the cui itself does not occupy an addressable memory location. when both ce# and we# go v il (valid), the command is written to cui and the address and data are latched on the rising edge of ce# or we#, whichever goes high first. the command can be written to the cui at the standard microprocessor writing timing. rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 18 4 command definitions operations of the device are selected by the specific commands written to the cui (command user interface). since commands are partition-specific, it is important to write commands within the target partition s address range (see table 5). each command except for the full chip erase command and otp program command affects only the mode of the partition to which the command is written. 4.1 read array command upon initial device power-up or after reset mode, all the partitions in the device default to asynchronous read mode in which 8-word page mode is available. the read array command to a partition places the partition to read array mode. the partition remains enabled for read array mode until another valid command is written to the partition. when rst# is at v ih , the read array command is valid independent of the voltage on v pp . once the internal wsm (write state machine) has started block erase, full chip erase, (page buffer) program or otp program in one partition, the partition will not recognize the read array command until the wsm completes its operation or unless the wsm is suspended via the block erase suspend or (page buffer) program suspend command. however, the read array command can be accepted in other partitions except for full chip erase or otp program operation. since lh28f320bx/lh28f640bx series provide dual work capability, partitions not executing block erase or (page buffer) program operation are allowed to set to the read array mode and the memory array data within the partitions can be read without suspending block erase or (page buffer) program operation. 4.2 read identifier codes/otp command the read identifier codes/otp mode is initiated by writing the read identifier codes/otp command (90h) to the target partition. read operations to that partition output the identifier codes or the data within the otp block. to terminate the operation, write another valid command to the partition. in this mode, the manufacturer code, device code, block lock configuration codes, read configuration register code, partition configuration register code and the data within the otp block as well as the otp block lock state can be read on the addresses shown in table 6 through table 8. once the internal wsm has started block erase, full chip erase, (page buffer) program or otp program in one partition, the partition will not recognize the read identifier codes/ otp command until the wsm completes its operation or unless the wsm is suspended via the block erase suspend or (page buffer) program suspend command. however, the read identifier codes/otp command can be accepted in other partitions except for full chip erase or otp program operation. like the read array command, the read identifier codes/otp command functions independently of the v pp voltage and rst# must be at v ih . to read the data in the otp block, it is important to write addresses within the otp area s address range (refer to table 6 through table 8). asynchronous page mode and synchronous burst mode are not available for reading identifier codes/otp. read operations for identifier codes or otp block support single asynchronous read cycle or single synchronous read cycle. rev. 2.20 synchronous burst mode will be available for future device. appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 19 notes: 1. bus operations are defined in table 4. 2. first bus cycle command address should be the same as the second cycle address. x=any valid address within the device. pa=address within the selected partition. ia=identifier codes address (see table 6 through table 8). qa=query codes address. refer to appendix of lh28f320bx/lh28f640bx series for details. ba=address within the block being erased, set/cleared block lock bit or set block lock-down bit. wa=address of memory location for the program command or the first address for the page buffer program command. oa=address of otp block to be read or programmed (see figure 4). rcrc=read configuration register code presented on the addresses a 0 -a 15 . pcrc=partition configuration register code presented on the address a 0 -a 15 . 3. id=data read from identifier codes. (see table 6 through table 8). qd=data read from query database. refer to appendix of lh28f320bx/lh28f640bx series for details. srd=data read from status register. see table 9 for a description of the status register bits. wd=data to be programmed at location wa. data is latched on the rising edge of we# or ce# (whichever goes high first). od=data to be programmed at location oa. data is latched on the rising edge of we# or ce# (whichever goes high first). n-1=n is the number of the words to be loaded into a page buffer. 4. following the read identifier codes/otp command, read operations access manufacturer code, device code, block lock configuration code, read configuration register code, partition configuration register code and the data within otp block (see table 6 through table 8). the read query command is available for reading cfi (common flash interface) information. 5. block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. unlocked block can be erased or programmed when rst# is v ih . 6. either 40h or 10h are recognized by the cui (command user interface) as the program setup. table 5.command definitions (11) commandbus cycles req d notesfirst bus cyclesecond bus cycle oper (1) addr (2) data (3) oper (1) addr (2) data (3) read array12writepaffh read identifier codes/otp 22,3,4writepa90hreadia or oaid or od read query 22,3,4writepa98hreadqaqd read status register22,3writepa70hreadpasrd clear status register12writepa50h block erase22,3,5writeba20hwritebad0h full chip erase22,5,9writex30hwritexd0h program22,3,5,6writewa40h or 10h writewawd page buffer program 42,3,5,7writewae8hwritewan-1 block erase and (page buffer) program suspend 12,8,9writepab0h block erase and (page buffer) program resume 12,8,9writepad0h set block lock bit22writeba60hwriteba01h clear block lock bit22,10writeba60hwritebad0h set block lock-down bit22writeba60hwriteba2fh otp program22,3,9writeoac0hwriteoaod set read configuration register22,3writercrc60hwritercrc03h set partition configuration register 22,3writepcrc60hwritepcrc04h rev. 2.20 synchronous burst mode will be available for future device. appendix to spec no.:mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 20 7. following the third bus cycle, inputs the program sequential address and write data of "n" times. finally, input the any valid address within the target partition to be programmed and the confirm command (d0h). refer to appendix of lh28f320bx/lh28f640bx series for details. 8. if the program operation in one partition is suspended and the erase operation in other partition is also suspended, the suspended program operation should be resumed first, and then the suspended erase operation should be resumed next. 9. full chip erase and otp program operations can not be suspended. the otp program command can not be accepted while the block erase operation is being suspended. 10. following the clear block lock bit command, block which is not locked-down is unlocked when wp# is v il . when wp# is v ih , lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration. 11. commands other than those shown above are reserved by sharp for future device implementations and should not be used. rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 21 notes: 1. the address a 20 -a 16 to read the manufacturer, device, lock configuration, device configuration code and otp data are shown in below table. 2. top parameter device has its parameter blocks in the plane3 (the highest address). 3. bottom parameter device has its parameter blocks in the plane0 (the lowest address) 4. dq 15 -dq 2 is reserved for future implementation. 5. rcrc=read configuration register code. 6. pcrc=partition configuration register code. 7. otp-lk=otp block lock configuration. 8. otp=otp block data. notes: 1. the address to read the identifier codes or otp data is dependent on the partition which is selected when writing the read identifier codes/otp command (90h). table 6.identifier codes and otp address for read operation code address [a 15 -a 0 ] (1) data [dq 15 -dq 0 ] notes manufacturer codemanufacturer code0000h00b0h device code (32m-bit device) 32m top parameter device code0001h00b4h2 32m bottom parameter device code 0001h00b5h3 device code (64m-bit device) 64m top parameter device code0001h00b0h2 64m bottom parameter device code 0001h00b1h3 block lock configuration code block is unlocked block address + 2 dq 0 = 0 4 block is lockeddq 0 = 1 4 block is not locked-downdq 1 = 0 4 block is locked-downdq 1 = 1 4 device configuration coderead configuration register0005hrcrc5 partition configuration register0006hpcrc6 otpotp lock0080hotp-lk7 otp 0081-0088hotp8 table 7.identifier codes and otp address for read operation on partition configuration (1) for 32m-bit device partition configuration registeraddress (32m-bit device) pcr.10pcr.9pcr.8 [a 20 -a 16 ] 00000h 00100h or 08h 01000h or 10h 10000h or 18h 01100h or 08h or 10h 11000h or 10h or 18h 10100h or 08h or 18h 11100h or 08h or 10h or 18h rev. 2.20 synchronous burst mode will be available for future device. appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 22 notes: 1. the address to read the identifier codes or otp data is dependent on the partition which is selected when writing the read identifier codes/otp command (90h). table 8.identifier codes and otp address for read operation on partition configuration (1) for 64m-bit device partition configuration registeraddress (64m-bit device) pcr.10pcr.9pcr.8 [a 21 -a 16 ] 00000h 00100h or 10h 01000h or 20h 10000h or 30h 01100h or 10h or 20h 11000h or 20h or 30h 10100h or 10h or 30h 11100h or 10h or 20h or 30h rev. 2.20 appendix to spec no.:mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 23 4.3 read query command the read query mode is initiated by writing the read query command (98h) to the target partition. read operations to that partition output the query code (common flash interface code) shown in section 6. to terminate the operation, write another valid command to the partition. once the internal wsm has started block erase, full chip erase, (page buffer) program or otp program in one partition, the partition will not recognize the read query command until the wsm completes its operation or unless the wsm is suspended via the block erase suspend or (page buffer) program suspend command. however, the read query command can be accepted in other partitions except for full chip erase or otp program operation. like the read array command, the read query command functions independently of the v pp voltage and rst# must be at v ih . refer to section 6 for more information about query code. asynchronous page mode and synchronous burst mode are not available for reading query code. read operations for query code support single asynchronous read cycle or single synchronous read cycle. 4.4 read status register command the status register may be read to determine when block erase, full chip erase, (page buffer) program or otp program has been completed and whether the operation has been successfully completed or not (see table 9). the status register can be read at any time by writing the read status register command (70h) to the target partition. subsequent read operations to that partition output the status register data until another valid command is written. the status register contents are latched on the falling edge of oe# or ce# whichever occurs later. oe# or ce# must toggle to v ih before further reads to update the status register latch. the read status register command functions independently of the v pp voltage and rst# must be at v ih . asynchronous page mode and synchronous burst mode are not available for reading status register. read operations for status register support single asynchronous read cycle or single synchronous read cycle. during the dual work operation, the status register data is read from the partition which is executing block erase or (page buffer) program operation. the memory array data can be read from other partitions which are not executing block erase or (page buffer) program operation. the partition to be accessed is automatically identified according to the input address. 4.5 clear status register command status register bits sr.5, sr.4, sr.3 and sr.1 that have been set to "1"s by the wsm can only be cleared by writing the clear status register command (50h). this command functions independently of the v pp voltage. rst# must be at v ih . to clear the status register, write the clear status register command and an address within the target partition to the cui. status register bits sr.5, sr.4, sr.3 and sr.1 indicate various error conditions occurring after writing commands (see table 9). when erasing multiple blocks or programming several words in sequence, clear these bits before starting each operation. the status register bits indicate an error for during the sequence. after executing the clear status register command, the partition returns to read array mode. this command clears only the status register of the addressed partition. during block erase suspend or (page buffer) program suspend, the clear status register command is invalid and the status register cannot be cleared. rev. 2.20 synchronous burst mode will be available for future device. appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 24 table 9.status register definition rrrrrrrr 15141312111098 wsmsbessbefcespbpopsvppspbpssdpsr 76543210 sr.15 - sr.8 = reserved for future enhancements (r) sr.7 = write state machine status (wsms) ? 1 = ready ? 0 = busy sr.6 = block erase suspend status (bess) ? 1 = block erase suspended ? 0 = block erase in progress/completed sr.5 = block erase and full chip erase status (befces) ? 1 = error in block erase or full chip erase ? 0 = successful block erase or full chip erase sr.4 = (page buffer) program and otp program status (pbpops) ? 1 = error in (page buffer) program or otp program ? 0 = successful (page buffer) program or otp program sr.3 = v pp status (vpps) ? 1 = v pp low detect, operation abort ? 0 = v pp ok sr.2 = (page buffer) program suspend status (pbpss) ? 1 = (page buffer) program suspended ? 0 = (page buffer) program in progress/completed sr.1 = device protect status (dps) ? 1 = erase or program attempted on a locked block, operation abort ? 0 = unlocked sr.0 = reserved for future enhancements (r) notes: status register indicates the status of the partition, not wsm (write state machine). even if the sr.7 is "1", the wsm may be occupied by the other partition when the device is set to 2, 3 or 4 partitions configuration. check sr.7 to determine block erase, full chip erase, (page buffer) program or otp program completion. sr.6 - sr.0 are invalid while sr.7="0". if both sr.5 and sr.4 are "1"s after a block erase, full chip erase, page buffer program, set/clear block lock bit, set block lock-down bit or set read/partition configuration register attempt, an improper command sequence was entered. sr.3 does not provide a continuous indication of v pp level. the wsm interrogates and indicates the v pp level only after block erase, full chip erase, (page buffer) program or otp program command sequences. sr.3 is not guaranteed to report accurate feedback when v pp v pph1 , v pph2 or v pplk . sr.1 does not provide a continuous indication of block lock bit. the wsm interrogates the block lock bit only after block erase, full chip erase, (page buffer) program or otp program command sequences. it informs the system, depending on the attempted operation, if the block lock bit is set. reading the block lock configuration codes after writing the read identifier codes/otp command indicates block lock bit status. sr.15 - sr.8 and sr.0 are reserved for future use and should be masked out when polling the status register. rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 25 table 10.extended status register definition rrrrrrrr 15141312111098 smsrrrrrrr 76543210 xsr.15-8 = reserved for future enhancements (r) xsr.7 = state machine status (sms) ? 1 = page buffer program available ? 0 = page buffer program not available xsr.6-0 = reserved for future enhancements (r) notes: after issue a page buffer program command (e8h), xsr.7=1 indicates that the entered command is accepted. if xsr.7 is "0", the command is not accepted and a next page buffer program command (e8h) should be issued again to check if page buffer is available or not. xsr.15-8 and xsr.6-0 are reserved for future use and should be masked out when polling the extended status register. rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 26 4.6 block erase command the two-cycle block erase command initiates one block erase at the addressed block within the target partition. read operations to that partition output the status register data of its partition. at the first cycle, command (20h) and an address within the block to be erased is written to the cui, and command (d0h) and the same address as the first cycle is written at the second cycle. once the block erase command is successfully written, the wsm automatically starts erase and verification processes. the data in the selected block are erased (becomes ffffh). the system cpu can detect the block erase completion by analyzing the output data of the status register bit sr.7. the partition including the block to be erased remains in read status register mode after the completion of the block erase operation until another command is written to the cui. figure 5.1 and figure 5.2 show a flowchart of the block erase operation. check the status register bit sr.5 at the end of block erase. if a block erase error is detected, the status register should be cleared before system software attempts corrective actions. the partition remains in read status register mode until a new command is written to that partition. this two-cycle command sequence ensures that block contents are not accidentally erased. an invalid block erase command sequence will result in status register bits sr.5 and sr.4 of the partition being set to "1" and the operation will be aborted. for reliable block erase operation, apply the specified voltage on v cc and v pph1/2 on v pp . in the absence of this voltage, block erase operations are not guaranteed. for example, attempting a block erase at v pp v pplk causes sr.5 and sr.3 being set to "1". also, successful block erase requires that the selected block is unlocked. when block erase is attempted to the locked block, bits sr.5 and sr.1 will be set to "1". block erase operation may occur in only one partition at a time. other partitions must be in one of the read modes. 4.7 full chip erase command the two-cycle full chip erase command erases all of the unlocked blocks. before writing this command, all of the partitions should be ready (wsm should not be occupied by any partition). at the first cycle, command (30h) is written to the cui, and command (d0h) is written at the second cycle. after writing the command, the device outputs the status register data when any address within the device is selected. the wsm automatically starts the erase operation for all unlocked blocks, skipping the locked blocks. the full chip erase operation cannot be suspended through the erase suspend command (described later). the system cpu can detect the full chip erase completion by analyzing the output data of the status register bit sr.7. all the partitions remain in the read status register mode after the completion of the full chip erase operation until another command is written to the cui. figure 6.1 and figure 6.2 show a flowchart of the full chip erase operation. the wsm aborts the operation upon encountering an error during the full chip erase operation and leaves the remaining blocks not erased. after the full chip erase operation, check the status register bit sr.5. when a full chip erase error is detected, sr5 of all partitions will be set to "1". the status registers for all partitions should be cleared before system software attempts corrective actions. after that, retry the full chip erase command or erase block by block using the block erase command. this two-cycle command sequence ensures that block contents are not accidentally erased. an invalid full chip erase command sequence will result in status register bits sr.5 and sr.4 of all partitions being set to "1" and the operation will be aborted. for reliable full chip erase operation, apply the specified voltage on v cc and v pph1/2 on v pp . in the absence of this voltage, full chip erase operations are not guaranteed. for example, attempting a full chip erase at v pp v pplk causes sr.5 and sr.3 being set to "1". as previously mentioned, the full chip erase command erases all blocks except for the locked blocks. unlike the block erase, the status register bits sr.5 and sr.1 are not set to "1" even if the locked block is included. however, when all blocks are locked, the bits sr.5 and sr.1 are set to "1" and the operation will not be executed. if an error is detected during the full chip erase operation, error bits for all status registers are set to "1". this requires that the clear status register command be written to all partitions to clear the error bits. dual work operation is not available during the full chip erase mode. the memory array data cannot be read in this mode. to return to the read array mode, write the read array command (ffh) to the cui after the completion of the full chip erase operation. rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 27 bus operation commandcomments writeblock erase data=20h addr=within block to be erased data=d0h addr=within block to be erased read status register data addr=within block to be erased standby check sr.7 1=wsm ready 0=wsm busy when subsequently erasing a block, repeat the above sequence. full status check can be done after each block erase or after a sequence of block erasures. write ffh after a sequence of block erasures to place device in read array mode. bus operation commandcomments write read status register data=70h addr=within partition read status register data addr=within partition standby check sr.7 1=wsm ready 0=wsm busy standby check sr.6 1=block erase suspended 0=block erase completed standby check sr.2 1=(page buffer) program suspended 0=(page buffer) program completed rev. 2.20 figure 5.1.automated block erase flowchart appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 28 figure 5.2.automated block erase flowchart (continued) rev. 2.20 bus operation commandcomments standby check sr.3 1=v pp error detect standby check sr.1 1=device protect detect block lock bit is set. standby check sr.4,5 both 1=command sequence error standby check sr.5 1=block erase error sr.5, sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple blocks are erased before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 29 bus operation commandcomments write full chip erase data=30h addr=x data=d0h addr=x read status register data addr=x standby check sr.7 1=wsm ready 0=wsm busy check the status after full chip erase. write ffh after the full chip erase to place device in read array mode. bus operation commandcomments write read status register data=70h addr=within partition read status register data addr=within partition standby check sr.7 1=wsm ready 0=wsm busy standby check sr.6 1=block erase suspended 0=block erase completed standby check sr.2 1=(page buffer) program suspended 0=(page buffer) program completed figure 6.1.automated full chip erase flowchart rev. 2.20 appendix to spec no.:mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 30 bus operation commandcomments standby check sr.3 1=v pp error detect standby check sr.1 1=device protect detect all blocks are locked. standby check sr.4,5 both 1=command sequence error standby check sr.5 1=full chip erase error sr.5, sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple blocks are erased before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. figure 6.2.automated full chip erase flowchart (continued) rev. 2.20 appendix to spec no.:mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 31 4.8 program command a two-cycle command sequence written to the target partition initiates a word program operation. read operations to the target partition to be programmed output the status register data until another valid command is written. at the first cycle, write command (standard 40h or alternate 10h) and an address of memory location to be programmed, followed by the second write that specifies the address and data. the wsm then takes over, controlling the internal word program algorithm. the system cpu can detect the word program completion by analyzing the output data of the status register bit sr.7. figure 7.1 and figure 7.2 show a program flowchart. the internal wsm verify only detects errors for "1"s that are not successfully programmed to "0"s. check the status register bit sr.4 at the end of word program. if a word program error is detected, the status register should be cleared before system software attempts corrective actions. the partition remains in read status register mode until it receives another command. for reliable word program operation, apply the specified voltage on v cc and v pph1/2 on v pp . in the absence of this voltage, word program operations are not guaranteed. for example, attempting a word program at v pp v pplk causes sr.4 and sr.3 being set to "1". also, successful word program requires for the selected block is unlocked. when word program is attempted to the locked block, bits sr.4 and sr.1 will be set to "1". word program operation may occur in only one partition at a time. other partitions must be in one of the read modes. 4.9 page buffer program command the lh28f320bx/lh28f640bx series has two planes of 16-word page buffer, which can perform fast sequential programming up to 32 words. the data are once loaded to the page buffer and programmed to the flash array when the confirm command (d0h) is written. see the flowchart in figure 8.1 and figure 8.2. the page buffer program is executed by at least four- cycle or up to 19-cycle command sequence. first, write the page buffer program setup command (e8h) and start address to the partition s cui. at this point, read operations to the target partition to be programmed output the extended status register data (see table 10). check the extended status register data. if the extended status register bit xsr 7 is "0", no page buffer is available and page buffer program setup command which has just been written is ignored. to retry, continue monitoring xsr.7 by writing page buffer program setup (e8h) with program address until xsr.7 transitions to "1". when xsr.7 transitions to "1", the setup command written is valid. then, at the second cycle, write the word count [n]-1 and start address if the number of words to be programmed is [n] in total. that is, when the number of [n] is 1 word, write (00h); if [n] is 16 words, write (0fh). the word count [n]-1 must be less than or equal to 0fh. attempting to write more than 0fh for the word count causes the sequence error and the status register bits sr.5 and sr.4 are set to "1". after writing a word count [n]-1, read operations to the target partition to be programmed output the status register data. at the third cycle following the write of [n]-1, write the first data to be programmed and start address to the partition s cui. lower 4 bits (a 0 -a 3 ) of the start address also correspond to the page buffer address and the data are stored in the page buffer. at the fourth and subsequent cycles, write additional data and address, depending on the count. all subsequent address must lie within the start address plus the count. after writing the nth word data, write the confirm command (d0h) and an address within the target partition at the last cycle. this initiates the wsm to being transferring the data from the page buffer to the flash array. if a command other than the confirm command (d0h) is written, sequence error occurs and status register bits sr.5 and sr.4 of the partition are set to "1". when the data are transferred from the page buffer to the flash array, the status register bit sr.7 is set to "0". then, the target partition is in the page buffer program busy mode. rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 32 for additional page buffer program, write another page buffer program setup command (e8h) and check xsr.7. the page buffer program command can be queued while wsm is busy as long as xsr.7 indicates "1", because lh28f320bx/lh28f640bx series has two buffers. if an error occurs while programming, the device will stop programming and flush next page buffer program command which has been previously queued. status register bit sr.4 is set to "1". sr.4 should be cleared before writing next command. if the page buffer program command is attempted past an erase block boundary, the device will program the data to the flash array up to an erase block boundary and then stop programming. the status register bits sr.5 and sr.4 will be set to "1" (command sequence error). sr.5 and sr.4 should be cleared before writing next command. for reliable page buffer program operation, apply the specified voltage on v cc and v pph1/2 on v pp . in the absence of this voltage, page buffer program operations are not guaranteed. for example, attempting a page buffer program at v pp v pplk causes sr.4 and sr.3 being set to "1". also, successful page buffer program requires for the selected block is unlocked. when page buffer program is attempted to the locked block, bits sr.4 and sr.1 will be set to "1". during page buffer program, dual work operation is available. the array data can be read from partitions not being programmed. page buffer program operation may occur in only one partition at a time. other partitions must be in one of the read modes. rev. 2.20 appendix to spec no.:mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 33 bus operation commandcomments write word program data=40h or 10h addr= location to be programmed data= data to be programmed addr= location to be programmed read status register data addr= location to be programmed standby check sr.7 1=wsm ready 0=wsm busy repeat the above sequence for the subsequent word programs. sr full status check can be done after each word program, or after a sequence of word programs. write ffh after a sequence of word programs to place device in read array mode. bus operation commandcomments write read status register data=70h addr=within partition read status register data addr=within partition standby check sr.7 1=wsm ready 0=wsm busy standby check sr.2 1=program suspended 0=program completed figure 7.1.automated program flowchart rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 34 bus operation commandcomments standby check sr.3 1=v pp error detect standby check sr.1 1=device protect detect block lock bit is set. standby check sr.4 1=word program error sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple locations are programmed before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. figure 7.2.automated program flowchart (continued) rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 35 bus operation commandcomments write page buffer program data=e8h addr=start address read extended status register data standby check xsr.7 1=page buffer program ready 0=page buffer program busy write (note 1) page buffer program data=[word count n]-1 addr=start address write (note 2, 3) data=buffer data addr=start address write (note 4, 5) <(n+2)th cycle> data=buffer data addr=sequential address following start address write <(n+3)th cycle> data=d0h addr=within partition read status register data addr=within partition standby check sr.7 1=wsm ready 0=wsm busy 1. word count values on dq 0-7 are loaded into count register. 2. write buffer contents will be programmed at the start address. 3. align the start address on a write buffer boundary for maximum programming performance. 4. the device aborts the page buffer program command if the current address is outside of the original block address. 5. the status register indicates an improper command sequence if the page buffer program command is aborted. follow this with a clear status register command. sr full status check can be done after each page buffer program, or after a sequence of page buffer programs. write ffh after the last page buffer program operation to place device in read array mode. figure 8.1.automated page buffer program flowchart rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 36 bus operation commandcomments write read status register data=70h addr=within partition read status register data addr=within partition standby check sr.7 1=wsm ready 0=wsm busy standby check sr.2 1=program suspended 0=program completed bus operation commandcomments standby check sr.3 1=v pp error detect standby check sr.1 1=device protect detect block lock bit is set. standby check sr.4,5 both 1=command sequence error standby check sr.4 1=page buffer program error sr.5,sr.4,sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple locations are programmed before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. figure 8.2.automated page buffer program flowchart (continued) rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 37 4.10 block erase suspend command and block erase resume command the block erase suspend command (b0h) allows block erase interruption to read or program data in the blocks other than that which is suspended. this command is valid for the block erase operation and the full chip erase operation can not be suspended. once the block erase process starts in a partition, writing the block erase suspend command to the partition requests that the wsm suspends the block erase sequence at a predetermined point in the algorithm. read operations to the target partition after writing the block erase suspend command access the status register. status register bits sr.7 and sr.6 indicate if the block erase operation has been suspended (both will be set to "1"). specification t whrh2 or t ehrh2 defines the block erase suspend latency. when the block erase suspend command is written after the completion of the block erase operation, the partition returns to read array mode. therefore, the read status register command (70h) must be written to the target partition after writing the block erase suspend command. if the status register bits sr.7 and sr.6 are set to "1", block erase has been suspended. at this point, a read array command can be written to read data from blocks other than that which is suspended. a (page buffer) program command sequence can also be written during block erase suspend to program data in other blocks. using the (page buffer) program suspend command (see section 4.11), a program operation can also be suspended during a block erase suspend. during a word program operation with block erase suspended, status register bit sr.7 will return to "0". however, sr.6 will remain "1" to indicate the block erase suspend status. if the page buffer program setup command (e8h) is written to the target partition during block erase suspend in which sr.7 and sr.6 are set to "1", read operations to the target partition to be programmed output the extended status register data. in read extended status register mode, bit xsr.7 is only valid, which indicates that the written command (e8h) is available, and other bits (from xsr.6 to xsr.0) are invalid (see table 10). when writing the word count [n]-1 and start address at next command cycle, the target partition returns to read status register mode and the status register bits sr.7 and sr.6 are set to "1". after the page buffer program confirm command (d0h) is written, the status register bit sr.7 will return to "0". however, sr.6 will remain "1" to indicate the block erase suspend status. the only other valid commands while block erase is suspended are read identifier codes/otp, read query, read status register, set block lock bit, clear block lock bit, set block lock-down bit, set read configuration register and block erase resume command. to resume the block erase operation, write the block erase resume command (d0h) to the partition. status register bits sr.7 and sr.6 will be automatically cleared. after the block erase resume command is written, the target partition automatically outputs the status register data when read. v pp must remain at v pph1/2 (at the same level before block erase suspended) while block erase is suspended. rst# must remain at v ih and wp# must also remain at v il or v ih (at the same level before block erase suspended). block erase cannot resume until (page buffer) program operation initiated during block erase suspend is completed. figure 9 shows the block erase suspend and block erase resume flowchart. if the interval time from a block erase resume command to a subsequent block erase suspend command is shorter than t eres and its sequence is repeated, the block erase operation may not be finished. rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 38 bus operation commandcomments write block erase suspend data=b0h addr=within partition write read status register data=70h addr=within partition read status register data addr=within partition standby check sr.7 1=wsm ready 0=wsm busy standby check sr.6 1=block erase suspended 0=block erase completed write block erase resume data=d0h addr=within block to be suspended figure 9.block erase suspend and block erase resume flowchart rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 39 4.11 (page buffer) program suspend command and (page buffer) program resume command the (page buffer) program suspend command (b0h) allows word and page buffer program interruption to read data from locations other than that which is suspended. once the (page buffer) program process starts in a partition, writing the (page buffer) program suspend command to the partition requests that the wsm suspends the (page buffer) program sequence at a predetermined point in the algorithm. read operations to the target partition after writing the (page buffer) program suspend command access the status register. status register bits sr.7 and sr.2 indicate if the (page buffer) program operation has been suspended (both will be set to "1"). specification t whrh1 or t ehrh1 defines the (page buffer) program suspend latency. when the (page buffer) program suspend command is written after the completion of the (page buffer) program operation, the partition returns to read array mode. therefore, the read status register command (70h) must be written to the target partition after writing the (page buffer) program suspend command. if the status register bits sr.7 and sr.2 are set to "1", (page buffer) program has been suspended. at this point, a read array command can be written to read data from locations other than that which is suspended. the only other valid commands while (page buffer) program is suspended are read identifier codes/otp, read query, read status register, set read configuration register and (page buffer) program resume command. to resume the (page buffer) program operation, write the (page buffer) program resume command (d0h) to the partition. status register bits sr.7 and sr.2 will be automatically cleared. after the (page buffer) program resume command is written, the target partition automatically outputs the status register data when read. v pp must remain at v pph1/2 (at the same level before (page buffer) program suspended) while (page buffer) program is suspended. rst# must remain at v ih and wp# must also remain at v il or v ih (at the same level before (page buffer) program suspended). figure 10 shows the (page buffer) program suspend and (page buffer) program resume flowchart. if the interval time from a (page buffer) program resume command to a subsequent (page buffer) program suspend command is short and its sequence is repeated, the (page buffer) program operation may not be finished. after the (page buffer) program suspend command is written to the 1st partition to suspend the program operation while the 2nd partition is in block erase suspend mode, the (page buffer) program resume command should be written to the 1st partition first to resume the suspended (page buffer) program operation. after that, the block erase resume command is written to the 2nd partition to resume the suspended block erase operation. if the block erase resume command is written before the (page buffer) program resume command, the block erase resume command is ignored and the partition to which the block erase resume command is written is set to read array mode with block erase suspended. rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 40 bus operation commandcomments write (page buffer) program suspend data=b0h addr=within partition write read status register data=70h addr=within partition read status register data addr=within partition standby check sr.7 1=wsm ready 0=wsm busy standby check sr.2 1=(page buffer) program suspended 0=(page buffer) program completed write data=ffh addr=within partition read read array locations from block other than that being programmed write (page buffer) program resume data=d0h addr=location to be suspended figure 10.(page buffer) program suspend and (page buffer) program resume flowchart rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 41 4.12 set block lock bit command the lh28f320bx/lh28f640bx series is provided with a block lock bit for each parameter block and main block. the features of set block lock bit is as follows: ? any block can be independently locked by setting its block lock bit. ? the time required for block locking is less than the minimum command cycle time (minimum time from the rising edge of ce# or we# to write the command to the next rising edge of ce# or we#). ? block erase, full chip erase or (page buffer) program on a locked block cannot be executed (see table 11 and table 12). ? at power-up or device reset, all blocks default to locked state, regardless of the states before power-off or reset operation. (lock bit is volatile.) the set block lock bit command is a two-cycle command. at the first cycle, command (60h) and an address within the block to be locked is written to the target partition. at the second cycle, command (01h) and the same address as the first cycle is written. read operations to the target partition output the status register data until another valid command is written. after writing the second cycle command, the block lock bit is set within the minimum command cycle time and the corresponding block is locked. to check the lock status, write the read identifier codes/otp command (90h) and an address within the target block. subsequent reads at block base address +2 (see table 6 through table 8) will output the lock/unlock status of that block. the lock/unlock status is represented by the output pin dq 0 . if the output of dq 0 is "1", the block lock bit is set correctly. figure 11 shows set block lock bit flowchart. the two-cycle command sequence ensures that block is not accidentally locked. an invalid set block lock bit command sequence will result in both status register bits sr.5 and sr.4 being set to "1" and the operation will not be executed. the set block lock bit command is available when the power supply voltage is specified level, independent of the voltage on v pp . at power-up or device reset, since all blocks default to locked state, write the clear block lock bit command described later to clear block lock bit before a erase or program operation. rev. 2.20 notes: 1. otp (one time program) block has the lock function which is different from those described above. 2. dq 0 =1: a block is locked; dq 0 =0: a block is unlocked. dq 1 =1: a block is locked-down; dq 1 =0: a block is not locked-down. 3. erase and program are general terms, respectively, to express: block erase, full chip erase and (page buffer) program operations. 4. at power-up or device reset, all blocks default to locked state and are not locked-down, that is, [001] (wp#=0) or [101] (wp#=1), regardless of the states before power-off or reset operation. 5. when wp# is driven to v il in [110] state, the state changes to [011] and the blocks are automatically locked. table 11.functions of block lock (1) and block lock-down current state erase/program allowed? (3) statewp# dq 1 (2) dq 0 (2) state name [000]000unlockedyes [001] (4) 001lockedno [011]011locked-downno [100]100unlockedyes [101] (4) 101lockedno [110] (5) 110lock-down disableyes [111]111lock-down disableno appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 42 notes: 1. "set lock" means set block lock bit command, "clear lock" means clear block lock bit command and "set lock-down" means set block lock-down bit command. 2. when the set block lock-down bit command is written to the unlocked block (dq 0 =0), the corresponding block is locked-down and automatically locked at the same time. 3. "no change" means that the state remains unchanged after the command written. 4. in this state transitions table, assumes that wp# is not changed and fixed v il or v ih . notes: 1. "wp#=0 1" means that wp# is driven to v ih and "wp#=1 0" means that wp# is driven to v il 2. state transition from the current state [011] to the next state depends on the previous state. 3. when wp# is driven to v il in [110] state, the state changes to [011] and the blocks are automatically locked. 4. in this state transitions table, assumes that lock configuration commands are not written in previous, current and next state. table 12.block locking state transitions upon command write (4) current stateresult after lock command written (next state) statewp# dq 1 dq 0 set lock (1) clear lock (1) set lock-down (1) [000]000[001]no change [011] (2) [001]001 no change (3) [000][011] [011]011no changeno changeno change [100]100[101]no change [111] (2) [101]101no change[100][111] [110]110[111]no change [111] (2) [111]111no change[110]no change table 13.block locking state transitions upon wp# transition (4) previous state current stateresult after wp# transition (next state) statewp# dq 1 dq 0 wp#=0 1 (1) wp#=1 0 (1) -[000]000[100]- -[001]001[101]- [110] (2) [011]011 [110]- other than [110] (2) [111]- -[100]100-[000] -[101]101-[001] -[110]110- [011] (3) -[111]111-[011] rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 43 bus operation commandcomments write set block lock bit/set block lock- down bit data=60h addr=within block to be locked or locked-down data= 01h (lock bit), or 2fh(lock-down bit) addr=within block to be locked or locked-down read status register data addr=within partition standby check sr.4, 5 both 1=command sequence error writeread id code data=90h addr=within partition read lock bit or lock-down bit data addr=block address+2 (see table 6 through table 8) standby check dq 0 /dq 1 1=lock bit or lock-down bit is set repeat for the subsequent set block lock/lock-down bit. lock status check can be done after each set block lock/ lock-down bit operation or after a sequence of set block lock/lock-down bit operations. sr.5 and sr.4 are only cleared by the clear status register command in cases where multiple block lock/ lock-down bits are set before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. write ffh after a sequence of set block lock/lock-down bit operations to place device in read array mode. bus operation commandcomments write read status register data=70h addr=within partition read status register data addr=within partition standby check sr.7 1=wsm ready 0=wsm busy figure 11.set block lock bit and set block lock-down bit flowchart rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 44 4.13 clear block lock bit command a locked block can be unlocked by writing the clear block lock bit command. the features of clear block lock bit is as follows: ? any block can be independently unlocked by clearing its block lock bit. ? the time required to be unlocked is less than the minimum command cycle time (minimum time from the rising edge of ce# or we# to write the command to the next rising edge of ce# or we#). ? block erase, full chip erase or (page buffer) program on an unlocked block can be executed (see table 11 and table 12). the clear block lock bit command is a two-cycle command. at the first cycle, command (60h) and an address within the block to be unlocked is written to the target partition. at the second cycle, command (d0h) and the same address as the first cycle is written. read operations to the target partition output the status register data until another valid command is written. after writing the second cycle command, the block lock bit is cleared within the minimum command cycle time and the corresponding block is unlocked. to check the unlock status, write the read identifier codes/otp command (90h) and an address within the target block. subsequent reads at block base address +2 (see table 6 through table 8) will output the lock/unlock status of that block. the lock/unlock status is represented by the output pin dq 0 . if the output of dq 0 is "0", the block lock bit is cleared correctly. figure 12 shows clear block lock bit flowchart. the two-cycle command sequence ensures that block is not accidentally unlocked. an invalid clear block lock bit command sequence will result in both status register bits sr.5 and sr.4 being set to "1" and the operation will not be executed. the clear block lock bit command is available when the power supply voltage is specified level, independent of the voltage on v pp . 4.14 set block lock-down bit command the block lock-down bit, when set, increases the security for data protection. the block lock-down bit has the following functions. ? any block can be independently locked-down by setting its block lock-down bit. ? the time required to be locked-down is less than the minimum command cycle time (minimum time from the rising edge of ce# or we# to write the command to the next rising edge of ce# or we#). ? locked-down block is automatically locked regardless of wp# at v il or v ih . ? when wp# is v il , locked-down blocks are protected from lock status changes. ? when wp# is v ih , the lock-down bits are disabled and locked-down blocks can be individually unlocked by software command. these blocks can then be re-locked and unlocked as desired while wp# remains v ih . when wp# goes v il , blocks that were previously marked lock-down return to the lock-down state regardless of any changes made while wp# was v ih (see table 13). ? at power-up or device reset, all blocks are not locked- down regardless of the states before power-off or reset operation. (lock-down bit is volatile.) ? lock-down bit cannot be cleared by software, only by power-off or device reset. the set block lock-down bit command is a two-cycle command. at the first cycle, command (60h) and an address within the block to be locked-down is written to the target partition. at the second cycle, command (2fh) and the same address as the first cycle is written. read operations to the target partition output the status register data until another valid command is written. after writing the second cycle command, the block lock-down bit is set within the minimum command cycle time and the corresponding block is locked-down. to check the lock- down status, write the read identifier codes/otp command (90h) and an address within the target block. subsequent reads at block base address +2 (see table 6 through table 8) will output the lock/unlock status of that block. the lock-down status is represented by the output pin dq 1 . if the output of dq 1 is "1", the block lock-down bit is set correctly. figure 11 shows set block lock-down bit flowchart. rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 45 bus operation commandcomments write clear block lock bit data=60h addr=within block to be unlocked data= d0h addr=within block to be unlocked read status register data addr=within partition standby check sr.4, 5 both 1=command sequence error writeread id code data=90h addr=within partition read lock bit data addr=block address+2 (see table 6 through table 8) standby check dq 0 0=lock bit is cleared repeat for the subsequent clear block lock bit. lock status check can be done after each clear block lock bit operation or after a sequence of clear block lock bit operations. sr.5 and sr.4 are only cleared by the clear status register command in cases where multiple block lock bits are cleared before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. write ffh after a sequence of clear block lock bit operations to place device in read array mode. bus operation commandcomments write read status register data=70h addr=within partition read status register data addr=within partition standby check sr.7 1=wsm ready 0=wsm busy figure 12.clear block lock bit flowchart rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 46 the two-cycle command sequence ensures that block is not accidentally locked-down. an invalid set block lock-down bit command sequence will result in both status register bits sr.5 and sr.4 being set to "1" and the operation will not be executed. the set block lock-down bit command is available when the power supply voltage is specified level, independent of the voltage on v pp . at power-up or device reset, since no blocks are locked- down, write the set block lock-down bit command as necessary. while wp# is v ih , the lock-down bits are disabled but not cleared. once any block is locked-down, it cannot be cleared until power-off or device reset. 4.15 otp program command otp program is executed by a two-cycle command sequence. at the first cycle, command (c0h) and an address within the otp block (see figure 4) is written, followed by the second write that specifies the address and data. after writing the command, the device outputs the status register data when any address within the device is selected. the wsm then takes over, controlling the internal otp program algorithm. the system cpu can detect the otp program completion by analyzing the output data of the status register bit sr.7. figure 13.1 and figure 13.2 show otp program flowchart. the address written at the command cycle must be the address within the otp block (refer to figure 4). writing an address outside the otp block will cause a otp program error and the status register bit sr.4 is set to "1". clear the status register before writing next command. the internal wsm verify only detects errors for "1"s that are not successfully programmed to "0"s. check the status register bit sr.4 at the end of otp program. if a otp program error is detected, the status register should be cleared before system software attempts corrective actions. for reliable otp program operation, apply the specified voltage on v cc and v pph1/2 on v pp . in the absence of this voltage, otp program operations are not guaranteed. for example, attempting an otp program at v pp v pplk causes sr.4 and sr.3 being set to "1". otp program operation on locked area causes sr.4 and sr.1 being set to "1" and the operation will not be executed. otp program cannot be suspended through the (page buffer) program suspend command (b0h). even if the (page buffer) program suspend command is written during otp program operation, the suspend command will be ignored. if an error is detected during the otp program operation, error bits for all status registers are set to "1". this requires that the clear status register command be written to all partitions to clear the error bits. dual work operation is not available while the otp program mode, and the memory array data cannot be read even if that operation has been completed. to return to the read array mode, write the read array command (ffh) to the partition s cui after the completion of the otp program operation. rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 47 bus operation commandcomments write otp program data=c0h addr=location to be programmed write data=data to be programmed addr=location to be programmed read status register data addr=x standby check sr.7 1=wsm ready 0=wsm busy repeat for subsequent otp program. sr full status check can be done after each otp program, or after a sequence of otp programs. write ffh after the otp program operation to place device in read array mode. bus operation commandcomments write read status register data=70h addr=within partition read status register data addr=within partition standby check sr.7 1=wsm ready 0=wsm busy figure 13.1.automated otp program flowchart rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 48 bus operation commandcomments standby check sr.3 1=v pp error detect standby check sr.1 1=device protect detect standby check sr.4 1=otp program error sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple locations are programmed before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. figure 13.2.automated otp program flowchart (continued) rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 49 4.16 set read configuration register command the read configuration register (rcr) bits are set by writing the set read configuration register command to the device. this operation is initiated by a two-cycle command sequence. the read configuration register can be configured by writing the command with the read configuration register code. at the first cycle, command (60h) and a read configuration register code is written. at the second cycle, command (03h) and the same address as the first cycle is written. the read configuration register code is placed on the address bus, a 15 - a 0 , and is latched on the rising edge of adv#, ce#, or we# (whichever occurs first). the read configuration register code sets the device s read configuration, burst order, frequency configuration, and burst length. this command functions independently of the v pp voltage. rst# must be at v ih . after executing this command, the partition returns to read array mode. the read configuration register bits rcr.13-11, rcr.9, rcr.8, rcr.7, rcr.6, rcr.3 and rcr.2-0 are only valid for synchronous burst mode. figure 16 shows set read configuration register flowchart. notes: ? the read configuration register code can be read via the read identifier codes/otp command (90h). address 0005h on a 15 - a 0 contains the read configuration register code (see table 6 through table 8). ? all the bits in the read configuration register are set to "1" after device power-up or reset. (read configuration register bits are volatile.) 4.16.1 device read configuration (read mode) each partition supports a high performance synchronous burst mode read configuration. the read configuration register bit rcr.15 sets the device read configuration (read mode; see table 14). all the parameter and main blocks support asynchronous read mode, asynchronous 8-word page mode and synchronous burst mode configuration. status register, query code, identifier codes, otp block and configuration register codes can only be read in single asynchronous or single synchronous read mode. rev. 2.20 figure 14.frequency configuration synchronous burst mode will be available for future device. appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 50 table 14.read configuration register definition rmrfc2fc1fc0rdocwc 15141312111098 bsccrrbwbl2bl1bl0 76543210 rcr.15 = read mode (rm) ? 0 = synchronous burst reads enabled ? 1 = asynchronous reads enabled (default) rcr.14 = reserved for future enhancements (r) rcr.13-11 = frequency configuration (fc2-0) ? 000 = code 0 reserved for future use ? 001 = code 1 reserved for future use ? 010 = code 2 ? 011 = code 3 ? 100 = code 4 ? 101 = code 5 ? 110 = code 6 reserved for future use ? 111 = code 7 reserved for future use (default) rcr.10 = reserved for future enhancements (r) rcr.9 = data output configuration (doc) ? 0 = hold data for one clock ? 1 = hold data for two clocks (default) rcr.8 = wait# configuration (wc) ? 0 = wait# asserted during delay ? 1 = wait# asserted one data cycle before delay (default) rcr.7 = burst sequence (bs) ? 0 = intel burst order ? 1 = linear burst order (default) rcr.6 = clock configuration (cc) ? 0 = burst starts and data output on falling clock edge ? 1 = burst starts and data output on rising clock edge (default) rcr.5-4 = reserved for future enhancements (r) rcr.3 = burst wrap (bw) ? 0 = wrap burst reads within burst length set by rcr.2-0 ? 1 = no wrap burst reads within burst length set by rcr.2-0 (default). rcr.2-0 = burst length (bl2-0) ? 001 = 4 word burst ? 010 = 8 word burst ? 011 = reserved for future use ? 111 = continuous (linear) burst (default) notes: read configuration register affects the read operations from main and parameter blocks. read operations for status register, query code, identifier codes, otp block and device configuration codes support single read cycles. rcr.14, rcr.10, rcr.5 and rcr.4 bits are reserved for future use. refer to frequency configuration in section 4.16.2 for information about the frequency configuration rcr.13-11. undocumented combinations of bits rcr.13-11 are reserved by sharp corporation for future implementations and should not be used. refer to section 4.16.7 for information about burst wrap configuration rcr.3. in the asynchronous page mode, the burst length always equals 8 words. all the bits in the read configuration register are set to "1" after power-up or device reset. when the bit rcr.15 is set to "1", other bits are invalid. rev. 2.20 synchronous burst mode will be available for future device. appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 51 4.16.2 frequency configuration the read configuration register bits rcr.13, rcr.12 and rcr.11 indicates the frequency configuration (see table 14). the frequency configuration informs the number of clocks that must elapse after adv# is driven active (v il ) before data will be available. this value is determined by the input clock frequency. see table 15 for the specific input clk frequency configuration. figure 14 shows data output latency from adv# going v il for different frequency configuration codes. 4.16.3 data output configuration the data output configuration, shown by rcr.9 (see table 14), determines the number of clocks that data will be held valid. the data hold time for the lh28f320bx/ lh28f640bx series can be set to one clock or two clocks (see figure 15). table 15.frequency configuration settings read configuration register frequency configuration code input clock frequency rcr.13rcr.12rcr.11tbd nstbd ns 0102 24mhz tbd mhz 0113 36mhz tbd mhz 1004 40mhz tbd mhz 1015 tbd mhz tbd mhz rev. 2.20 figure 15.output configuration synchronous burst mode will be available for future device. appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 52 4.16.4 wait# configuration the wait# configuration bit rcr.8 (see table 14) controls the wait# output signal. this output signal can be set to be asserted during or one clk cycle before an output delay occurs, when the burst read crosses the first 64-word boundary in continuous burst length or the 4- or 8-word burst length with no-wrap mode. its setting will depend on the system and cpu characteristic. 4.16.5 burst sequence the burst sequence bit rcr.7 (see table 14) determines the order in which data is addressed in synchronous burst mode. this order is configurable to either linear or intel burst order. the continuous burst length only supports linear burst order. the order will be determined by the cpu characteristic. refer to table 16 for linear burst order and intel burst order in detail. 4.16.6 clock configuration the clock configuration bit rcr.6 (see table 14) configures the device to start a burst cycle, output data, and assert wait# on the rising or falling edge of the clock. this clk flexibility enables interfacing the lh28f320bx/lh28f640bx series flash memory to a wide range of burst cpus. 4.16.7 burst wrap the burst wrap bit rcr.3 (see table 14) determines the wrap mode as follows. ? 4- or 8-word burst-accesses are performed within the burst-length boundary in wrap mode (rcr.3="0"). ? 4- or 8-word and continuous burst-accesses cross the burst-length boundaries in no-wrap mode (rcr.3="1"). no-wrap mode is only valid for linear burst order (rcr.7="1"). no-wrap mode (rcr.3="1") enables wait# to hold off the system processor, as it does in the continuous burst mode. in the no-wrap mode, the device operates similar to continuous linear burst mode but consumes less power during 4- and 8-word bursts. refer to table 16 for burst wrap in detail. for example, if rcr.3="0" (wrap mode) and rcr.2- 0=001 (4-word burst length), then possible linear burst sequences are 0-1-2-3, 1-2-3-0, 2-3-0-1 and 3-0-1-2. if rcr.3="1" (no-wrap mode) and rcr.2-0=001 (4- word burst length), then possible linear burst sequences are 0-1-2-3, 1-2-3-4, 2-3-4-5 and 3-4-5-6. no-wrap mode not only enables limited non-aligned sequential burst, but also reduces power by minimizing the number of internal read operations. 4.16.8 burst length the burst length is the number of words that the device will output. the read configuration register bits rcr.2-0 (see table 14) set the burst length. the lh28f320bx/ lh28f640bx series supports burst lengths of four and eight words. it also supports a continuous burst mode. in continuous burst mode, the device will linearly output data until the internal burst counter reaches the end of the device's burst-able address space or a partition boundary. refer to table 16 for burst length in detail. 4.16.8.1 continuous burst length in continuous burst mode or 4-, 8-word burst with no- wrap (rcr.3="1") mode, the flash memory may cause an output delay when the burst read crosses the first 64-word boundary. it depends on the starting address whether an output delay will occur or not. when the starting address is aligned to a 64-word boundary, the delay will not occur. if the starting address is the end of a 64-word boundary, the output delay will be equal to the frequency configuration setting; this is the worst case delay. the delay will only take place once during a continuous burst access. if the burst read never crosses a 64-word boundary, the delay will never happen. the wait# output pin is used in continuous burst mode or 4-, 8-word burst with no-wrap mode to inform the system if this output delay occurs. rev. 2.20 synchronous burst mode will be available for future device. appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 53 note: 1. the burst wrap bit (rcr.3) determines whether 4- or 8-word burst-accesses wrap within the burst-length boundary or whether they cross word-length boundaries to perform linear accesses. in the no-wrap mode (rcr.3=1), the device operates similar to continuous linear burst mode but consumes less power during 4- and 8-word bursts. table 16.read sequence and burst length starting address [decimal] burst wrap (1) (rcr.3=) burst addressing sequence [decimal] 4-word burst length (rcr.2-0=001) 8-word burst length (rcr.2-0=010) cotinuous burst (rcr.2-0=111) linearintellinearintellinear 000-1-2-30-1-2-30-1-2-3-4-5-6-70-1-2-3-4-5-6-70-1-2-3-4-5-6 101-2-3-01-0-3-21-2-3-4-5-6-7-01-0-3-2-5-4-7-61-2-3-4-5-6-7 202-3-0-12-3-0-12-3-4-5-6-7-0-12-3-0-1-6-7-4-52-3-4-5-6-7-8 303-0-1-23-2-1-03-4-5-6-7-0-1-23-2-1-0-7-6-5-43-4-5-6-7-8-9 404-5-6-7-0-1-2-34-5-6-7-0-1-2-34-5-6-7-8-9-10 505-6-7-0-1-2-3-45-4-7-6-1-0-3-25-6-7-8-9-10-11 606-7-0-1-2-3-4-56-7-4-5-2-3-0-16-7-8-9-10-11-12 707-0-1-2-3-4-5-67-6-5-4-3-2-1-07-8-9-10-11-12-13 . . . . . . . . . . . . . . . . . . . . . 14014-15-16-17-18-19-20 15015-16-17-18-19-20-21 . . . . . . . . . . . . . . . . . . . . . 010-1-2-3na0-1-2-3-4-5-6-7na0-1-2-3-4-5-6 111-2-3-4na1-2-3-4-5-6-7-8na1-2-3-4-5-6-7 212-3-4-5na2-3-4-5-6-7-8-9na2-3-4-5-6-7-8 313-4-5-6na3-4-5-6-7-8-9-10na3-4-5-6-7-8-9 414-5-6-7-8-9-10-11na4-5-6-7-8-9-10 515-6-7-8-9-10-11-12na5-6-7-8-9-10-11 61 6-7-8-9-10-11-12- 13 na6-7-8-9-10-11-12 71 7-8-9-10-11-12-13- 14 na7-8-9-10-11-12-13 . . . . . . . . . . . . . . . . . . . . . 14114-15-16-17-18-19-20 15115-16-17-18-19-20-21 rev. 2.20 synchronousburstmodewillbeavailable forfuture device. appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 54 bus operation commandcomments write set read configuration register, set partition configuration register data=60h addr=configuration register code (see table 14 or table 17) data= 03h (read configuration), or 04h(partition configuration) addr=configuration register code (see table 14 or table 17) write read status register data=70h addr=within partition read status register data addr=within partition standby check sr.4, 5 both 1=command sequence error writeread id code data=90h addr=within partition read read/partition configuration register code addr=0005h/0006h (see table 6 through table 8) standby check dq 15 -dq 0 for read/ partition configuration register code configuration register code can be read after set read/ partition configuration register operation. sr.5 and sr.4 are only cleared by the clear status register command. if an error is detected, clear the status register before attempting retry or other error recovery. after a successful set read/partition configuration register operation, the device returns to read array mode. bus operation commandcomments write read status register data=70h addr=within partition read status register data addr=within partition standby check sr.7 1=wsm ready 0=wsm busy figure 16.set read configuration register and set partition configuration register flowchart rev. 2.20 synchronousburstmodewillbeavailable forfuture device. appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 55 4.17 set partition configuration register command the partition configuration register (pcr) bits are set by writing the set partition configuration register command to the device. this operation is initiated by a two-cycle command sequence. the partition configuration register can be configured by writing the command with the partition configuration register code. at the first cycle, command (60h) and a partition configuration register code is written. at the second cycle, command (04h) and the same address as the first cycle is written. the partition configuration register code is placed on the address bus, a 15 - a 0 , and is latched on the rising edge of adv#, ce#, or we# (whichever occurs first). the partition configuration register code sets the partition boundaries. this command functions independently of the v pp voltage. rst# must be at v ih . after executing this command, the device returns to read array mode and status registers are cleared. figure 16 shows set partition configuration register flowchart. notes: ? the partition configuration register code can be read via the read identifier codes/otp command (90h). address 0006h on a 15 - a 0 contains the partition configuration register code (see table 6 through table 8). ? partition configuration after device power-up or reset is as follows. (partition configuration register bits are volatile.) plane 0-2 are merged into one partition. (top parameter device) plane1-3 are merged into one partition. (bottom parameter device) 4.17.1 partition configuration the partition configuration shown in table 17 determines the partiton boundaries for the dual work (simultaneous read while erase/program) operation. the partition boundaries can be set to any plane boundaries. if the partition configuration register bits pcr.10-8 (pc.2-0) are set to "001", the partition boundary is set between plane0 and plane1. there are two partitions in this configuration. plane1-3 are merged to one partition. status registers for plane1-3 are also merged to one. if the partition configuration register bits are set to "101", the partition boundaries are set between plane0 and plane1 and between plane2 and plane3. there are three partitions in this configuration. plane1-2 are merged to one partition. if the partition configuration register bits are set to "111", there are four partitions. each partition is just the same as each plane. figure 17 illustrates the various partition configuration. rev. 2.20 appendix to spec no.: mfm2-j13222model no.: LRS1382 march 1, 2001
fum00701 56 table 17.partition configuration register definition rrrrrpc2pc1pc0 15141312111098 rrrrrrrr 76543210 pcr.15-11 = reserved for future enhancements (r) pcr.10-8 = partition configuration (pc2-0) ? 000 = no partitioning. dual work is not allowed. ? 001 = plane1-3 are merged into one partition. (default in a bottom parameter device) ? 010 = plane 0-1 and plane2-3 are merged into one partition respectively. ? 100 = plane 0-2 are merged into one partition. (default in a top parameter device) ? 011 = plane 2-3 are merged into one partition. there are three partitions in this configuration. dual work operation is available between any two partitions. ? 110 = plane 0-1 are merged into one partition. there are three partitions in this configuration. dual work operation is available between any two partitions. ? 101 = plane 1-2 are merged into one partition. there are three partitions in this configuration. dual work operation is available between any two partitions. ? 111 = there are four partitions in this configuration. each plane corresponds to each partition respectively. dual work operation is available between any two partitions. pcr.7-0 = reserved for future enhancements (r) notes: 1. after power-up or device reset, pcr10-8 (pc2-0) is set to "001" in a bottom parameter device and "100" in a top parameter device. 2. see figure 17 for the detail on partition configuration. 3. pcr.15-11 and pcr.7-0 bits are reserved for future use. if these bits are read via the read identifier codes/otp command, the device may output "1" or "0" on these bits. rev. 2.20 figure 17.partition configuration appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 57 5 design considerations 5.1 hardware design considerations 5.1.1 control using rst#, ce# and oe# the device will often be used in large memory arrays. sharp provides three control input pins to accommodate multiple memory connection. three control input pins, rst#, ce# and oe# provide for: ? minimize the power consumption of the memory ? avoid data confliction on the data bus to effectively use these control input pins, access the desired memory by enabling the ce# through the address decoder. connect oe# to read# control signal of all memory devices and system. with these connections, the selected memory devices are activated and deselected memory devices are in standby mode. rst# should be connected to the system powergood signal to prevent unintended writes during system power transitions. powergood should toggle (once set to v il ) during system reset. 5.1.2 power supply decoupling flash memory s power switching characteristics require careful device decoupling for eliminating noises to the system power lines. system designers should consider standby current levels (i ccs ), active current levels (i ccr ) and transient peaks produced by falling and rising edges of ce# and oe#. transient current magnitudes depend on the device outputs capacitive and inductive loading. two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. each flash device should have a 0.1 f ceramic capacitor connected between each v cc , v ccq and gnd and between v pp and gnd (when v pp is used as 12v supply). these high-frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads. additionally, for every eight devices, a 4.7 f electrolytic capacitor should be placed at the array s power supply connection between v cc and gnd. these capacitors will overcome voltage slumps caused by circuit board trace inductance. 5.1.3 v pp traces on printed circuit boards the v pp pin on the lh28f320bx/lh28f640bx series flash memory is only used to monitor the power supply voltage and is not used for a power supply pin except for 12v supply. therefore, even when on-board writing to the flash memory on the system, it is not required to consider that v pp supplies the currents on the printed circuit boards. however, in erase or program operations with applying 12v 0.3v to v pp pin, v pp is used for the power supply pin. when executing these operations, v pp trace widths and layout should be similar to that of v cc to supply the flash memory cells current for erasing or programming. adequate v pp supply traces, and decoupling capacitors placed adjacent to the component, will decrease spikes and overshoots. 5.1.4 v cc , v pp , rst# transitions if v pp is lower than v pplk , v cc is lower than v lko , or rst# is not at v ih , block erase, full chip erase, (page buffer) program and otp program operation are not guaranteed. when v pp error is detected, the status register bits sr.5 or sr.4 (depending on the attempted operation) and sr.3 will be set to "1". if rst# transitions to v il during the block erase, full chip erase, (page buffer) program or otp program operation, the status register bit sr.7 will remain "0" until reset operation has been completed. then, the attempted operation will be aborted and the device will enter reset mode after the completion of the reset sequence. if rst# is taken v il during a block erase, full chip erase, (page buffer) program or otp program operation, the memory contents at the aborted location are no longer valid. therefore, the proper command must be written again. and also, if v cc transitions to lower than v lko during a block erase, full chip erase, (page buffer) program or otp program operation, the attempted operation will be aborted and the memory contents at the aborted location are no longer valid. write the proper command again after v cc transitions above v lko . rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 58 5.1.5 power-up/down protection the lh28f320bx/lh28f640bx series is designed to offer protection against accidental block erase, full chip erase, (page buffer) program, otp program due to noises during power transitions. when the device power-up, holding v pp and rst# to gnd until v cc has reached the specified level and in stable. for additional information, please refer to the ap-007-sw-e rst#, v pp electric potential switching circuit . after power-up, the lh28f320bx/lh28f640bx series defaults to the mode described in section 2.1. system designers must guard against spurious writes when v cc voltages are above v lko and v pp voltages are above v pplk , by referring to section 5.3 and the following design considerations. since both ce# and we# must be at v il for a command write, driving either signal to v ih will inhibit writes to the device. the cui architecture provides additional protection because alternation of memory contents can only occur after successful completion of the two-step command sequences. the individual block locking scheme, which enables each block to be independently locked, unlocked or locked- down, prevents the accidental data alternation. the device is also disabled until rst# is brought to v ih , regardless of the state of its control inputs. by holding the device in reset during power-up/down, invalid bus conditions can be masked, providing yet another level of memory protection. 5.1.6 power dissipation when designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. the lh28f320bx/lh28f640bx series nonvolatility increases usable battery life because data is retained when system power is removed. 5.1.7 automatic power savings automatic power savings (aps) provides low-power operation during active mode. aps mode allows the flash memory to put itself into a low current state when not being accessed. after data is read from the memory array and addresses not switching, the device enters the aps mode where typical i cc current is comparable to i ccs . the flash memory stays in this static state with outputs valid until a new location is read. standard address access timings (t avqv ) provide new data when addresses are changed. during dual work operation (one partition being erased or programmed, while other partitions are one of read modes), the device cannot enter the aps mode even if the input address remains unchanged. 5.1.8 reset operation during power-up/down or transitions of power supply voltage, hold the rst# pin at v il to protect data against noises which are caused by invalid bus conditions and initialize the internal circuitry in flash memory. bringing rst# to v il resets the internal wsm (write state machine) and sets the status register to 80h. after return from reset, a time t phqv is required until outputs are valid, and a delay, t phwl and t phel , is required before a write sequence can be initiated. after this wake-up interval, normal operation is restored. rev. 2.20 appendix to spec no.:mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 59 5.2 software design considerations 5.2.1 wsm (write state machine) polling the status register bit sr.7 provides a software method of detecting block erase, full chip erase, (page buffer) program and otp program completion. after the block erase, full chip erase, (page buffer) program or otp program command is written to the cui (command user interface), sr.7 goes to "0". it will return to "1" when the wsm (write state machine) has completed the internal algorithm. the status register bit sr.7 is "1" state when the device is in the following mode. ? the device can accept the next command. ? block erase is suspended and (page buffer) program operation is not executed. ? (page buffer) program is suspended. ? reset mode 5.2.2 attention to program operation do not re- program "0" data for the bit in which "0" has been already programmed. this re- program operation may generate the bit which cannot be erased. to change the data from "1" to "0", take the following steps. ? program "0" for the bit in which you want to change the data from "1" to "0". ? program "1" for the bit in which "0" has been already programmed. (when "1" is programmed, erase/program operations are not executed onto the memory cell in flash memory.) for example, changing the data from "10111101" to "10111100" requires "11111110" programmed. 5.3 data protection method noises having a level exceeding the limit specified in the specification may be generated under specific operating conditions on some systems. such noises, when induced onto we# signal or power supply, may be interpreted as false commands and causes undesired memory updating. to protect the data stored in the flash memory against unwanted writing, systems operating with the flash memory should have the following write protect designs, as appropriate: the below describes data protection method. 1) protection of data in each block ? ny locked block by setting its block lock bit is protected against the data alternation. when wp# is v il , any locked-down block by setting its block lock- down bit is protected from lock status changes. by using this function, areas can be defined, for example, program area (locked blocks), and data area (unlocked blocks). ? for detailed block locking scheme, refer to sections 4.12 to 4.14. 2) protection of data with v pp control ? when the level of v pp is lower than v pplk (v pp lockout voltage), write functions to all blocks including otp block are disabled. all blocks are locked and the data in the blocks are completely protected. 3) protection of data with rst# ? especially during power transitions such as power-up and power-down, the flash memory enters reset mode by bringing rst# to v il , which inhibits write operation to all blocks including otp block. ? for detailed description on rst# control, refer to section 5.1.5. protection against noises on we# signal to prevent the recognition of false commands as write commands, system designer should consider the method for reducing noises on we# signal. rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 60 5.4 high performance read mode 5.4.1 cpu compatibility lh28f320bx/lh28f640bx series supports two high- performance read modes for the parameter and main blocks: ? asynchronous read mode in which 8-word page mode is available ? synchronous burst mode these two read modes provide much higher read accesses than was previously used. the asynchronous read mode is suitable for non-clocked memory systems and is compatible with standard page- mode rom. if the memory subsystem has access to an external processor referenced clock, the synchronous burst mode is available for increased read performance. the clock frequency for synchronous burst mode is described in specifications. if the system cpu or asic does not support page-mode or burst accesses, single asynchronous and synchronous read modes can be used. it depends on the setting in the read configuration register which read mode is available. when the read configuration register bit rcr.15 is set to "1", the device is in asynchronous read mode. if the bit rcr.15 is set to "0", the device is in synchronous burst mode. upon reset, the device defaults to asynchronous read mode and is put into read array mode. 5.4.2 features of adv# and clk adv# and clk pins are important for synchronous burst mode. ? adv# can be derived from the processor s transaction start signal. if the processor does not have this type of signal, other standard cpu control signals can be used to control adv#. adv# must toggle to inform the flash memory to latch a new address. if this signal is not used in asynchronous read mode, ce# must toggle to inform the flash memory of a new address. ? clk can be derived from the processor s memory clock output. if the processor does not supply this control signal to the memory subsystem, the signal can be received from the clock signal generator through a clock buffer. this buffer minimizes clock load and skew. 5.4.3 address latch the internal address latch latches the address for read and write operations. the address latch is controlled by adv#. when adv# is v il , the latch is open. the latch closes when adv# is driven high or upon the first rising (or falling) edge of clk while adv# is v il . this stores the current address on the bus into the flash memory device and lets the address bus change without affecting the flash. this pin works the same in write operations; the address to be written to the cui is latched on the rising adv# edge. since write operations are asynchronous mode, clk is ignored and the address is not latched on the clock edge. in asynchronous read mode, the address latch does not need to be used but addresses must then stay stable during the entire read operation. if adv# is not used, which is fixed v il , in asynchronous mode, addresses are latched on the rising edge of ce# during reads and on the rising edge of ce# or we# whichever goes high first during writes. 5.4.4 using asynchronous page mode after initial power-up or reset mode, the device defaults to asynchronous read mode in which 8-word page mode is available. the asynchronous page mode is available for the parameter and main blocks, and is not supported from other locations within the device, such as the status register, identifier codes, otp block and query codes. in asynchronous page mode, clk is ignored and adv# must be held v il throughout the page access. holding adv# v il allows new page mode accesses. the initial valid address will store 8 words of data in the internal page buffer. each word is then output onto the data bus by toggling the address a 2-0 . if the asynchronous page mode is only used, clk and adv# can be tied to gnd . holding clk and adv# gnd will minimize the power consumed by these two pins and will simplify the interface, making it compatible with standard flash memory and industry standard page mode roms. with adv# at v il , the addresses cannot be latched into the device. therefore, addresses must stay valid throughout the entire read cycle until ce# goes to v ih . figure 18 shows a waveform for asynchronous page mode read timing with adv# held low. note that the address a 2-0 must be toggled to output the page-mode data. in asynchronous read mode, the output of wait# is fixed to v oh . rev. 2.20 synchronous burst mode will be available for future device. appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 61 5.4.5 using synchronous burst mode synchronous burst mode provides a performance increase over asynchronous read mode. it supports effective zero wait-state performance up to the frequency described in specifications. the synchronous burst mode is available for the parameter and main blocks, and is not supported from other locations within the device, such as the status register, identifier codes, otp block and query codes. it is not possible to do a synchronous burst read across the partition boundary. figure 19illustrates a waveform for synchronous burst mode read timing. the valid addresses are asserted, and then the device will output the first data after certain delay time. subsequent data will be output every clk cycle. there are two different considerations for an external interface logic whether or not the processor supports synchronous burst mode at boot-up. ? case 1, the processor does not support synchronous burst mode at boot-up, but rather boots up in asynchronous read mode. this is the initial mode of the flash memory, so no special design considerations need to be made. after booting up, the processor can configure the read configuration register for synchronous burst mode. ? case 2, the processor does support synchronous burst mode at boot-up. after return from reset, the flash memory defaults to asynchronous read mode, which is inherently slower than synchronous burst mode. external interface logic will be needed to inform the processor of this, and to insert wait states to match the flash memory s timing with the processor s timing. this logic is only necessary until the processor has a chance to set the flash memory device to synchronous burst mode, at which time the external logic must be notified of this change. this can be accomplished via a write-able register within the system wait-state logic or via a general purpose i/o (gpio) pin. the gpio pin may operate as an input into the system logic. 5.4.6 using wait# in burst mode lh28f320bx/lh28f640bx series supports 4-word, 8- word and continuous burst modes. in continuous burst mode or 4-, 8-word burst with no-wrap (rcr.3="1") mode, wait# informs the system cpu whether output data is valid or not (refer to section 4.16.8.1). ? wait#="1": there is valid data on the bus. ? wait#="0": the data on the bus is invalid. when the output delay is encountered, the wait# pin will be asserted at a logic "0". this signal should be fed into the systems wait-state control logic or directly to the cpu. the wait# output pin is gated by ce# and oe#. if either ce# or oe# go to v ih , the wait# output buffer turns off. an internal pull-up resistor holds wait# at a logic "1" state. figure 20 shows a waveform for an output delay timing with adv# at a logic "0". wait# can be configured for assertion during the delay or one data cycle before the delay by setting the read configuration register bit rcr.8. 5.4.7 single read mode the following data can only be read in single asynchronous read mode or single synchronous read mode. ? status register ? query code ? manufacturer code ? device code ? block lock configuration code ? read configuration register code ? partition configuration register code ? otp block a waveform of read timing for single asynchronous read mode and single synchronous read mode are shown in figure 21 and figure 22, respectively. single asynchronous read mode is compatible with previous sharp flash memory devices. clk is ignored in this mode. the valid addresses are asserted, and then the device will output data after certain delay time, such as t avqv , t vlqv , t elqv or t glqv . addresses are latched on the rising edge of adv#. if adv# is held v il , addresses must stay valid throughout the entire read cycle until ce# goes to v ih . in single synchronous read mode, after the valid addresses are asserted, the corresponding data will be output on the rising or falling edge of clk, which is determined by the read configuration register bit rcr.6. addresses are lathed when adv# is driven high or upon the rising or falling edge of clk while adv# is v il . 4- word, 8-word or continuous burst accesses is not available in this mode. therefore, the external input addresses must be incremented every read cycle. rev. 2.20 synchronous burst mode will be available for future device. appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 62 figure 18.ac waveform for asynchronous page mode read operations from main blocks or parameter blocks (a 21 is not used for 32m-bit device.) rev. 2.20 synchronous burst mode will be available for future device. appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 63 figure 19.ac waveform for synchronous burst mode read operations from main blocks or parameter blocks in 4-word burst mode: rcr.2-0=001 (a 21 is not used for 32m-bit device.) rev. 2.20 synchronous burst mode will be available for future device. synchronous burst mode will be available for future device. appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 64 figure 20.ac waveform for an output delay when continuous burst read with data output configurations set to one clock (a 21 is not used for 32m-bit device.) rev. 2.20 synchronous burst mode will be available for future device. appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 65 figure 21.ac waveform for single asynchronous read operations from status register, identifier codes, otp block or query code (a 21 is not used for 32m-bit device.) rev. 2.20 synchronous burst mode will be available for future device. appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 66 figure 22.ac waveform for single synchronous read operations from status register, identifier codes, otp block or query code (a 21 is not used for 32m-bit device.) rev. 2.20 synchronous burst mode will be available for future device. appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 67 6 common flash interface this section defines the data structure of the common flash interface (cfi) code, which is called query code. query code can be read by writing the read query command (98h) to the target partition s cui. system software should confirm this code to gain critical information such as block size, density, bit organization and electrical specifications. once this code has been obtained, the software will understand which command sets should be used to enable erases, programs and other operations for the flash memory device. the query code is part of an overall specification for multiple command set and control interface descriptions called common flash interface or cfi. common flash interface for the lh28f320bx/ lh28f640bx series is now under development. query code is described in the next version of appendix. rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001
fum00701 68 7 related document information (1) note: 1. international customers should contact their local sharp or distribution sales office. document no.document name ap-001-sd-e flash memory family software drivers ap-006-pt-e data protection method of sharp flash memory ap-007-sw-e rp#, v pp electric potential switching circuit rev. 2.20 appendix to spec no.: mfm2-j13222 model no.: LRS1382 march 1, 2001

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